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Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24648 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -394,6 +394,22 @@ public:
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Ops.push_back(Op5);
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return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
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}
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SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
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MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
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SDOperand Op3, SDOperand Op4, SDOperand Op5,
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SDOperand Op6) {
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std::vector<MVT::ValueType> ResultTys;
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ResultTys.push_back(VT1);
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ResultTys.push_back(VT2);
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std::vector<SDOperand> Ops;
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Ops.push_back(Op1);
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Ops.push_back(Op2);
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Ops.push_back(Op3);
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Ops.push_back(Op4);
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Ops.push_back(Op5);
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Ops.push_back(Op6);
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return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops);
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}
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SDOperand getTargetNode(unsigned Opcode, MVT::ValueType VT1,
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MVT::ValueType VT2, std::vector<SDOperand> &Ops) {
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std::vector<MVT::ValueType> ResultTys;
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@ -1165,11 +1165,14 @@ def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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} // end isConvertibleToThreeAddress
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} // end isCommutable
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def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2),
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"add{b} {$src2, $dst|$dst, $src2}", []>;
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"add{b} {$src2, $dst|$dst, $src2}",
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[(set R8:$dst, (add R8:$src1, (load addr:$src2)))]>;
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def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
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"add{w} {$src2, $dst|$dst, $src2}", []>, OpSize;
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"add{w} {$src2, $dst|$dst, $src2}",
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[(set R16:$dst, (add R16:$src1, (load addr:$src2)))]>, OpSize;
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def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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"add{l} {$src2, $dst|$dst, $src2}", []>;
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"add{l} {$src2, $dst|$dst, $src2}",
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[(set R32:$dst, (add R32:$src1, (load addr:$src2)))]>;
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def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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"add{b} {$src2, $dst|$dst, $src2}",
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