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https://github.com/RPCSX/llvm.git
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added suggesting color support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@673 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
parent
06faeee041
commit
ab304c42c2
@ -39,6 +39,9 @@ class LiveRange : public ValueSet
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// bool mustLoadFromStack; // must load from stack at start of method
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int SuggestedColor; // The suggested color for this LR
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public:
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@ -92,9 +95,27 @@ class LiveRange : public ValueSet
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}
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inline void setSuggestedColor(int Col) {
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//assert( (SuggestedColor == -1) && "Changing an already suggested color");
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if(SuggestedColor == -1 )
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SuggestedColor = Col;
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else if (DEBUG_RA)
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cout << "Already has a suggested color " << Col << endl;
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}
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inline unsigned getSuggestedColor() const {
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assert( SuggestedColor != -1); // only a valid color is obtained
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return (unsigned) SuggestedColor;
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}
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inline bool hasSuggestedColor() const {
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return ( SuggestedColor > -1);
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}
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inline LiveRange() : ValueSet() , CallInterferenceList()
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{
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Color = -1; // not yet colored
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Color = SuggestedColor = -1; // not yet colored
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mustSpill = mustSaveAcrossCalls = false;
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MyRegClass = NULL;
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UserIGNode = NULL;
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@ -42,7 +42,7 @@
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typedef hash_map <const Value *, LiveRange *, hashFuncValue> LiveRangeMapType;
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typedef vector <const Instruction *> CallRetInstrListType;
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class LiveRangeInfo
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{
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@ -56,7 +56,9 @@ private:
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const TargetMachine& TM; // target machine description
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vector<RegClass *> & RegClassList;// a vector containing register classess
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const MachineRegInfo& MRI; // machine reg info
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CallRetInstrListType CallRetInstrList; // a list of all call/ret instrs
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void unionAndUpdateLRs(LiveRange *L1, LiveRange *L2);
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@ -72,12 +74,22 @@ public:
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void constructLiveRanges();
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inline void addLRToMap(const Value *Val, LiveRange *LR) {
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assert( Val && LR && "Val/LR is NULL!\n");
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assert( (! LiveRangeMap[ Val ]) && "LR already set in map");
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LiveRangeMap[ Val ] = LR;
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}
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inline const LiveRangeMapType *const getLiveRangeMap() const
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{ return &LiveRangeMap; }
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inline LiveRange *getLiveRangeForValue( const Value *const Val)
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{ return LiveRangeMap[ Val ]; }
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inline CallRetInstrListType &getCallRetInstrList() {
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return CallRetInstrList;
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}
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@ -43,8 +43,8 @@
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class AddedInstrns
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{
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public:
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vector<const MachineInstr *> InstrnsBefore;
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vector<const MachineInstr *> InstrnsAfter;
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vector<MachineInstr *> InstrnsBefore;
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vector<MachineInstr *> InstrnsAfter;
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AddedInstrns() : InstrnsBefore(), InstrnsAfter() { }
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};
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@ -65,8 +65,8 @@ class PhyRegAlloc
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const MachineRegInfo &MRI; // Machine Register information
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const unsigned NumOfRegClasses; // recorded here for efficiency
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vector<const Instruction *> CallInstrList; // a list of all call instrs
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vector<const Instruction *> RetInstrList; // a list of all return instrs
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//vector<const Instruction *> CallInstrList; // a list of all call instrs
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//vector<const Instruction *> RetInstrList; // a list of all return instrs
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AddedInstrMapType AddedInstrMap; // to store instrns added in this phase
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@ -85,7 +85,9 @@ class PhyRegAlloc
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{ LRI.constructLiveRanges(); }
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void colorIncomingArgs();
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void colorCallRetArgs();
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void updateMachineCode();
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void printLabel(const Value *const Val);
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void printMachineCode();
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@ -39,6 +39,9 @@ class LiveRange : public ValueSet
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// bool mustLoadFromStack; // must load from stack at start of method
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int SuggestedColor; // The suggested color for this LR
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public:
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@ -92,9 +95,27 @@ class LiveRange : public ValueSet
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}
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inline void setSuggestedColor(int Col) {
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//assert( (SuggestedColor == -1) && "Changing an already suggested color");
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if(SuggestedColor == -1 )
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SuggestedColor = Col;
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else if (DEBUG_RA)
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cout << "Already has a suggested color " << Col << endl;
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}
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inline unsigned getSuggestedColor() const {
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assert( SuggestedColor != -1); // only a valid color is obtained
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return (unsigned) SuggestedColor;
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}
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inline bool hasSuggestedColor() const {
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return ( SuggestedColor > -1);
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}
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inline LiveRange() : ValueSet() , CallInterferenceList()
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{
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Color = -1; // not yet colored
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Color = SuggestedColor = -1; // not yet colored
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mustSpill = mustSaveAcrossCalls = false;
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MyRegClass = NULL;
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UserIGNode = NULL;
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@ -42,7 +42,7 @@
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typedef hash_map <const Value *, LiveRange *, hashFuncValue> LiveRangeMapType;
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typedef vector <const Instruction *> CallRetInstrListType;
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class LiveRangeInfo
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{
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@ -56,7 +56,9 @@ private:
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const TargetMachine& TM; // target machine description
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vector<RegClass *> & RegClassList;// a vector containing register classess
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const MachineRegInfo& MRI; // machine reg info
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CallRetInstrListType CallRetInstrList; // a list of all call/ret instrs
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void unionAndUpdateLRs(LiveRange *L1, LiveRange *L2);
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@ -72,12 +74,22 @@ public:
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void constructLiveRanges();
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inline void addLRToMap(const Value *Val, LiveRange *LR) {
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assert( Val && LR && "Val/LR is NULL!\n");
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assert( (! LiveRangeMap[ Val ]) && "LR already set in map");
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LiveRangeMap[ Val ] = LR;
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}
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inline const LiveRangeMapType *const getLiveRangeMap() const
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{ return &LiveRangeMap; }
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inline LiveRange *getLiveRangeForValue( const Value *const Val)
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{ return LiveRangeMap[ Val ]; }
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inline CallRetInstrListType &getCallRetInstrList() {
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return CallRetInstrList;
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}
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@ -43,8 +43,8 @@
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class AddedInstrns
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{
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public:
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vector<const MachineInstr *> InstrnsBefore;
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vector<const MachineInstr *> InstrnsAfter;
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vector<MachineInstr *> InstrnsBefore;
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vector<MachineInstr *> InstrnsAfter;
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AddedInstrns() : InstrnsBefore(), InstrnsAfter() { }
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};
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@ -65,8 +65,8 @@ class PhyRegAlloc
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const MachineRegInfo &MRI; // Machine Register information
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const unsigned NumOfRegClasses; // recorded here for efficiency
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vector<const Instruction *> CallInstrList; // a list of all call instrs
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vector<const Instruction *> RetInstrList; // a list of all return instrs
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//vector<const Instruction *> CallInstrList; // a list of all call instrs
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//vector<const Instruction *> RetInstrList; // a list of all return instrs
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AddedInstrMapType AddedInstrMap; // to store instrns added in this phase
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@ -85,7 +85,9 @@ class PhyRegAlloc
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{ LRI.constructLiveRanges(); }
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void colorIncomingArgs();
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void colorCallRetArgs();
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void updateMachineCode();
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void printLabel(const Value *const Val);
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void printMachineCode();
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@ -14,6 +14,7 @@
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Target/MachineSchedInfo.h"
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#include "llvm/CodeGen/RegClass.h"
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#include "llvm/Type.h"
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#include <sys/types.h>
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@ -95,6 +96,10 @@ public:
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return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
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}
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};
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@ -109,6 +114,8 @@ class UltraSparcRegInfo : public MachineRegInfo
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private:
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// The actual register classes in the Sparc
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enum RegClassIDs {
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IntRegClassID,
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FloatRegClassID,
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@ -116,6 +123,19 @@ class UltraSparcRegInfo : public MachineRegInfo
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FloatCCRegClassID
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};
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// Type of registers available in Sparc. There can be several reg types
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// in the same class. For instace, the float reg class has Single/Double
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// types
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enum RegTypes {
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IntRegType,
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FPSingleRegType,
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FPDoubleRegType,
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IntCCRegType,
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FloatCCRegType
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};
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// WARNING: If the above enum order must be changed, also modify
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// getRegisterClassOfValue method below since it assumes this particular
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// order for efficiency.
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@ -124,12 +144,11 @@ class UltraSparcRegInfo : public MachineRegInfo
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// reverse pointer to get info about the ultra sparc machine
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const UltraSparc *const UltraSparcInfo;
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// Int arguments can be passed in 6 int regs - %o0 to %o5 (cannot be changed)
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// Both int and float rguments can be passed in 6 int regs -
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// %o0 to %o5 (cannot be changed)
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unsigned const NumOfIntArgRegs;
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// Float arguments can be passed in this many regs - can be canged if needed
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// %f0 - %f5 are used (can hold 6 floats or 3 doubles)
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unsigned const NumOfFloatArgRegs;
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unsigned const InvalidRegNum;
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//void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
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@ -139,20 +158,85 @@ class UltraSparcRegInfo : public MachineRegInfo
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MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
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unsigned RegClassID) const ;
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Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
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int getRegType(const LiveRange *const LR) const {
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unsigned Typ;
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switch( (LR->getRegClass())->getID() ) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID:
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Typ = LR->getTypeID();
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if( Typ == Type::FloatTyID )
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return FPSingleRegType;
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else if( Typ == Type::DoubleTyID )
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return FPDoubleRegType;
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else assert(0 && "Unknown type in FloatRegClass");
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType ;
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default: assert( 0 && "Unknown reg class ID");
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}
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}
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int getRegType(const Value *const Val) const {
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unsigned Typ;
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switch( getRegClassIDOfValue(Val) ) {
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case IntRegClassID: return IntRegType;
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case FloatRegClassID:
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Typ = (Val->getType())->getPrimitiveID();
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if( Typ == Type::FloatTyID )
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return FPSingleRegType;
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else if( Typ == Type::DoubleTyID )
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return FPDoubleRegType;
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else assert(0 && "Unknown type in FloatRegClass");
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case IntCCRegClassID: return IntCCRegType;
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case FloatCCRegClassID: return FloatCCRegType ;
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default: assert( 0 && "Unknown reg class ID");
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}
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}
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MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
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const int RegType) const;
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MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
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const int RegType) const;
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public:
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UltraSparcRegInfo(const UltraSparc *const USI ) : UltraSparcInfo(USI),
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NumOfIntArgRegs(6),
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NumOfFloatArgRegs(6)
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NumOfFloatArgRegs(32),
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InvalidRegNum(1000)
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{
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MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
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MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
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MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
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"6 Float regs are used for float arg passing");
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assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
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"32 Float regs are used for float arg passing");
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}
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// ***** TODO Delete
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@ -172,7 +256,8 @@ class UltraSparcRegInfo : public MachineRegInfo
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unsigned res;
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if( ty && ty <= Type::LongTyID || (ty == Type::PointerTyID) )
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if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
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(ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
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res = IntRegClassID; // sparc int reg (ty=0: void)
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else if( ty <= Type::DoubleTyID)
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res = FloatRegClassID; // sparc float reg class
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@ -191,6 +276,7 @@ class UltraSparcRegInfo : public MachineRegInfo
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}
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// returns the register tha contains always zero
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// this is the unified register number
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inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
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// returns the reg used for pushing the address when a method is called.
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@ -202,18 +288,31 @@ class UltraSparcRegInfo : public MachineRegInfo
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// register contains the return value when a return instruction is reached.
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unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
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void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
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void suggestRegs4MethodArgs(const Method *const Meth,
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LiveRangeInfo& LRI) const;
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static void printReg(const LiveRange *const LR) ;
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void suggestRegs4CallArgs(const CallInst *const CallI,
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LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
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void colorCallArgs(vector<const Instruction *> & CallInstrList,
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LiveRangeInfo& LRI,
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AddedInstrMapType& AddedInstrMap ) const;
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void suggestReg4RetValue(const ReturnInst *const RetI,
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LiveRangeInfo& LRI) const;
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void colorRetArg(vector<const Instruction *> &
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RetInstrList, LiveRangeInfo& LRI,
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AddedInstrMapType &AddedInstrMap) const;
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void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
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AddedInstrns *const FirstAI) const;
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void colorCallArgs(const CallInst *const CallI, LiveRangeInfo& LRI,
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AddedInstrns *const CallAI) const;
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void colorRetValue(const ReturnInst *const RetI, LiveRangeInfo& LRI,
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AddedInstrns *const RetAI) const;
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bool handleSpecialMInstr(const MachineInstr * MInst,
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LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
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static void printReg(const LiveRange *const LR) ;
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// this method provides a unique number for each register
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inline int getUnifiedRegNum(int RegClassID, int reg) const {
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@ -226,6 +325,8 @@ class UltraSparcRegInfo : public MachineRegInfo
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return reg + 32 + 64; // 32 int, 64 float
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else if( RegClassID == IntCCRegClassID )
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return 4+ 32 + 64; // only int cc reg
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else if (reg==1000) //****** TODO: Remove
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return 1000;
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else
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assert(0 && "Invalid register class or reg number");
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@ -241,6 +342,9 @@ class UltraSparcRegInfo : public MachineRegInfo
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return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
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else if ( reg == 64+32+4)
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return "xcc"; // only integer cc reg
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else if (reg==1000) //****** TODO: Remove
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return "<*NoReg*>";
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else
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assert(0 && "Invalid register number");
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}
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