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[Hexagon] Generate hardware loop for a vectorized loop
The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brendon Cahoon
parent
49d3196418
commit
abf95a22c4
@ -1719,7 +1719,52 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
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// compared against an immediate, we can fix it.
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const RegisterBump &RB = I->second;
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if (CmpRegs.count(RB.first)) {
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if (!CmpImmOp)
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if (!CmpImmOp) {
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// If both operands to the compare instruction are registers, see if
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// it can be changed to use induction register as one of the operands.
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MachineInstr *IndI = nullptr;
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MachineInstr *nonIndI = nullptr;
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MachineOperand *IndMO = nullptr;
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MachineOperand *nonIndMO = nullptr;
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for (unsigned i = 1, n = PredDef->getNumOperands(); i < n; ++i) {
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MachineOperand &MO = PredDef->getOperand(i);
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if (MO.isReg() && MO.getReg() == RB.first) {
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DEBUG(dbgs() << "\n DefMI(" << i << ") = "
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<< *(MRI->getVRegDef(I->first)));
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if (IndI)
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return false;
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IndI = MRI->getVRegDef(I->first);
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IndMO = &MO;
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} else if (MO.isReg()) {
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DEBUG(dbgs() << "\n DefMI(" << i << ") = "
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<< *(MRI->getVRegDef(MO.getReg())));
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if (nonIndI)
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return false;
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nonIndI = MRI->getVRegDef(MO.getReg());
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nonIndMO = &MO;
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}
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}
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if (IndI && nonIndI &&
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nonIndI->getOpcode() == Hexagon::A2_addi &&
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nonIndI->getOperand(2).isImm() &&
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nonIndI->getOperand(2).getImm() == - RB.second) {
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bool Order = orderBumpCompare(IndI, PredDef);
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if (Order) {
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IndMO->setReg(I->first);
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nonIndMO->setReg(nonIndI->getOperand(1).getReg());
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return true;
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}
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}
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return false;
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}
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// It is not valid to do this transformation on an unsigned comparison
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// because it may underflow.
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Comparison::Kind Cmp = getComparisonKind(PredDef->getOpcode(), 0, 0, 0);
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if (!Cmp || Comparison::isUnsigned(Cmp))
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return false;
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// If the register is being compared against an immediate, try changing
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@ -1739,12 +1784,6 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
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if (!isImmValidForOpcode(PredDef->getOpcode(), CmpImm))
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return false;
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// It is not valid to do this transformation on an unsigned comparison
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// because it may underflow.
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Comparison::Kind Cmp = getComparisonKind(PredDef->getOpcode(), 0, 0, 0);
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if (!Cmp || Comparison::isUnsigned(Cmp))
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return false;
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// Make sure that the compare happens after the bump. Otherwise,
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// after the fixup, the compare would use a yet-undefined register.
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MachineInstr *BumpI = MRI->getVRegDef(I->first);
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93
test/CodeGen/Hexagon/hwloop5.ll
Normal file
93
test/CodeGen/Hexagon/hwloop5.ll
Normal file
@ -0,0 +1,93 @@
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; RUN: llc -O3 -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
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;
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; Generate hardware loop when unknown trip count loop is vectorized.
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; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}})
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; CHECK: endloop0
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; CHECK: loop0(.LBB{{[0-9]*}}_{{[0-9]*}}, r{{[0-9]+}})
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; CHECK: endloop0
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@A = common global [1000 x i32] zeroinitializer, align 8
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@B = common global [1000 x i32] zeroinitializer, align 8
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define i32 @dotprod2(i32 %count) #0 {
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entry.split:
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%cmp6 = icmp sgt i32 %count, 0
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br i1 %cmp6, label %polly.cond, label %for.end
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for.end.loopexit:
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br label %for.end
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for.end:
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%sum.0.lcssa.reg2mem.0.load37 = phi i32 [ 0, %entry.split ], [ %p_add34, %polly.loop_if13 ], [ %p_add, %for.end.loopexit ]
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ret i32 %sum.0.lcssa.reg2mem.0.load37
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polly.cond:
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%0 = icmp sgt i32 %count, 1
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br i1 %0, label %polly.loop_if, label %polly.loop_if13
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polly.loop_exit.loopexit:
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br label %polly.loop_exit
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polly.loop_exit:
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%1 = phi <2 x i32> [ zeroinitializer, %polly.loop_if ], [ %addp_vec, %polly.loop_exit.loopexit ]
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%2 = extractelement <2 x i32> %1, i32 0
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%3 = extractelement <2 x i32> %1, i32 1
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%add_sum = add i32 %2, %3
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br label %polly.loop_if13
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polly.loop_if:
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%4 = add i32 %count, -1
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%leftover_lb = and i32 %4, -2
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%polly.loop_guard = icmp eq i32 %leftover_lb, 0
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br i1 %polly.loop_guard, label %polly.loop_exit, label %polly.loop_preheader
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polly.stmt.for.body:
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%addp_vec28 = phi <2 x i32> [ zeroinitializer, %polly.loop_preheader ], [ %addp_vec, %polly.stmt.for.body ]
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%scevgep.phi = phi i32* [ getelementptr inbounds ([1000 x i32], [1000 x i32]* @A, i32 0, i32 0), %polly.loop_preheader ], [ %scevgep.inc, %polly.stmt.for.body ]
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%scevgep9.phi = phi i32* [ getelementptr inbounds ([1000 x i32], [1000 x i32]* @B, i32 0, i32 0), %polly.loop_preheader ], [ %scevgep9.inc, %polly.stmt.for.body ]
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%polly.indvar = phi i32 [ 0, %polly.loop_preheader ], [ %polly.indvar_next, %polly.stmt.for.body ]
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%vector_ptr = bitcast i32* %scevgep.phi to <2 x i32>*
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%_p_vec_full = load <2 x i32>, <2 x i32>* %vector_ptr, align 8
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%vector_ptr10 = bitcast i32* %scevgep9.phi to <2 x i32>*
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%_p_vec_full11 = load <2 x i32>, <2 x i32>* %vector_ptr10, align 8
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%mulp_vec = mul <2 x i32> %_p_vec_full11, %_p_vec_full
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%addp_vec = add <2 x i32> %mulp_vec, %addp_vec28
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%polly.indvar_next = add nsw i32 %polly.indvar, 2
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%polly.loop_cond = icmp eq i32 %polly.indvar, %polly.adjust_ub
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%scevgep.inc = getelementptr i32, i32* %scevgep.phi, i32 2
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%scevgep9.inc = getelementptr i32, i32* %scevgep9.phi, i32 2
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br i1 %polly.loop_cond, label %polly.loop_exit.loopexit, label %polly.stmt.for.body
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polly.loop_preheader:
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%polly.adjust_ub = add i32 %leftover_lb, -2
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br label %polly.stmt.for.body
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polly.loop_if13:
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%p_add34 = phi i32 [ 0, %polly.cond ], [ %add_sum, %polly.loop_exit ]
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%merge.lb = phi i32 [ 0, %polly.cond ], [ %leftover_lb, %polly.loop_exit ]
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%polly.loop_guard17 = icmp slt i32 %merge.lb, %count
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br i1 %polly.loop_guard17, label %polly.loop_preheader15, label %for.end
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polly.stmt.for.body22:
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%p_add30 = phi i32 [ %p_add34, %polly.loop_preheader15 ], [ %p_add, %polly.stmt.for.body22 ]
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%polly.indvar18 = phi i32 [ %merge.lb, %polly.loop_preheader15 ], [ %polly.indvar_next19, %polly.stmt.for.body22 ]
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%5 = tail call i32 @llvm.annotation.i32(i32 %polly.indvar18, i8* null, i8* null, i32 0), !polly.loop.smallTripCount !0
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%scevgep23 = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i32 %polly.indvar18
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%_p_scalar_ = load i32, i32* %scevgep23, align 4
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%scevgep24 = getelementptr [1000 x i32], [1000 x i32]* @B, i32 0, i32 %polly.indvar18
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%_p_scalar_25 = load i32, i32* %scevgep24, align 4
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%p_mul = mul nsw i32 %_p_scalar_25, %_p_scalar_
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%p_add = add nsw i32 %p_mul, %p_add30
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%polly.indvar_next19 = add nsw i32 %polly.indvar18, 1
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%polly.loop_cond21 = icmp slt i32 %polly.indvar18, %polly.adjust_ub20
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br i1 %polly.loop_cond21, label %polly.stmt.for.body22, label %for.end.loopexit
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polly.loop_preheader15:
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%polly.adjust_ub20 = add i32 %count, -1
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br label %polly.stmt.for.body22
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}
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declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1
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!0 = !{}
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