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Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93182 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1892,7 +1892,7 @@ def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
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def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
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(ins GR8 :$src1, i8imm:$src2),
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"or{b}\t{$src2, $dst|$dst, $src2}",
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[(set GR8:$dst, (or_not_add GR8:$src1, imm:$src2)),
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[(set GR8:$dst, (or GR8:$src1, imm:$src2)),
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(implicit EFLAGS)]>;
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def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
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(ins GR16:$src1, i16imm:$src2),
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@ -4663,9 +4663,6 @@ def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
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(SETB_C32r)>;
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// (or x, c) -> (add x, c) if masked bits are known zero.
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def : Pat<(parallel (or_is_add GR8:$src1, imm:$src2),
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(implicit EFLAGS)),
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(ADD8ri GR8:$src1, imm:$src2)>;
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def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
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(implicit EFLAGS)),
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(ADD16ri GR16:$src1, imm:$src2)>;
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