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[Sparc] Fix handling of double incoming arguments on sparc little-endian.
On SparcV8, doubles get passed in two 32-bit integer registers. The call code was already handling endianness correctly, but the incoming argument code was not -- it got the two halves in opposite order. Also remove some dead code in LowerFormalArguments_32 to handle less-than-32bit values, which can't actually happen. Finally, add some test cases for the 32-bit calling convention, cribbed from the 64abi.ll test, and run for both big and little-endian. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Y Knight
parent
03bb1cea0a
commit
ac785122ab
@ -400,6 +400,7 @@ LowerFormalArguments_32(SDValue Chain,
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CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
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const unsigned StackOffset = 92;
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bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
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unsigned InIdx = 0;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
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@ -442,6 +443,10 @@ LowerFormalArguments_32(SDValue Chain,
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&SP::IntRegsRegClass);
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LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
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}
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if (IsLittleEndian)
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std::swap(LoVal, HiVal);
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SDValue WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
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WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
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@ -498,6 +503,9 @@ LowerFormalArguments_32(SDValue Chain,
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MachinePointerInfo(),
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false, false, false, 0);
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if (IsLittleEndian)
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std::swap(LoVal, HiVal);
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SDValue WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
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WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
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@ -514,16 +522,12 @@ LowerFormalArguments_32(SDValue Chain,
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Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
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MachinePointerInfo(),
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false, false, false, 0);
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} else if (VA.getValVT() == MVT::f128) {
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report_fatal_error("SPARCv8 does not handle f128 in calls; "
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"pass indirectly");
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} else {
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ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
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// Sparc is big endian, so add an offset based on the ObjectVT.
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unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
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FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
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DAG.getConstant(Offset, dl, MVT::i32));
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Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
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MachinePointerInfo(),
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VA.getValVT(), false, false, false,0);
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Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
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// We shouldn't see any other value types here.
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assert(false && "Unexpected ValVT encountered in frame lowering.");
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}
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InVals.push_back(Load);
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}
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191
test/CodeGen/SPARC/32abi.ll
Normal file
191
test/CodeGen/SPARC/32abi.ll
Normal file
@ -0,0 +1,191 @@
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; RUN: llc < %s -march=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
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; RUN: llc < %s -march=sparcel -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
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; CHECK-LABEL: intarg:
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; The save/restore frame is not strictly necessary here, but we would need to
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; refer to %o registers instead.
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; CHECK: save %sp, -96, %sp
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; CHECK: ld [%fp+96], [[R2:%[gilo][0-7]]]
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; CHECK: ld [%fp+92], [[R1:%[gilo][0-7]]]
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; CHECK: stb %i0, [%i4]
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; CHECK: stb %i1, [%i4]
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; CHECK: sth %i2, [%i4]
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; CHECK: st %i3, [%i4]
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; CHECK: st %i4, [%i4]
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; CHECK: st %i5, [%i4]
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; CHECK: st [[R1]], [%i4]
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; CHECK: st [[R2]], [%i4]
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; CHECK: restore
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define void @intarg(i8 %a0, ; %i0
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i8 %a1, ; %i1
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i16 %a2, ; %i2
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i32 %a3, ; %i3
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i8* %a4, ; %i4
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i32 %a5, ; %i5
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i32 signext %a6, ; [%fp+92]
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i8* %a7) { ; [%fp+96]
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store i8 %a0, i8* %a4
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store i8 %a1, i8* %a4
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%p16 = bitcast i8* %a4 to i16*
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store i16 %a2, i16* %p16
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%p32 = bitcast i8* %a4 to i32*
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store i32 %a3, i32* %p32
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%pp = bitcast i8* %a4 to i8**
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store i8* %a4, i8** %pp
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store i32 %a5, i32* %p32
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store i32 %a6, i32* %p32
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store i8* %a7, i8** %pp
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ret void
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}
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; CHECK-LABEL: call_intarg:
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; CHECK: save %sp, -104, %sp
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; Use %o0-%o5 for outgoing arguments
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; CHECK: mov 5, %o5
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; CHECK: st %i0, [%sp+92]
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; CHECK: call intarg
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; CHECK-NOT: add %sp
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; CHECK: restore
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define void @call_intarg(i32 %i0, i8* %i1) {
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call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1)
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ret void
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}
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;; Verify doubles starting with an even reg, starting with an odd reg,
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;; straddling the boundary of regs and mem, and floats in regs and mem.
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;
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; CHECK-LABEL: floatarg:
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; CHECK: save %sp, -120, %sp
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; CHECK: mov %i5, %g2
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; CHECK-NEXT: ld [%fp+92], %g3
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; CHECK-NEXT: mov %i4, %i5
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; CHECK-NEXT: std %g2, [%fp+-24]
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; CHECK-NEXT: mov %i3, %i4
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; CHECK-NEXT: std %i4, [%fp+-16]
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; CHECK-NEXT: std %i0, [%fp+-8]
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; CHECK-NEXT: st %i2, [%fp+-28]
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; CHECK-NEXT: ld [%fp+104], %f0
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; CHECK-NEXT: ldd [%fp+96], %f2
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; CHECK-NEXT: ld [%fp+-28], %f1
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; CHECK-NEXT: ldd [%fp+-8], %f4
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; CHECK-NEXT: ldd [%fp+-16], %f6
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; CHECK-NEXT: ldd [%fp+-24], %f8
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; CHECK-NEXT: fstod %f1, %f10
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; CHECK-NEXT: faddd %f4, %f10, %f4
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; CHECK-NEXT: faddd %f6, %f4, %f4
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; CHECK-NEXT: faddd %f8, %f4, %f4
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; CHECK-NEXT: faddd %f2, %f4, %f2
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; CHECK-NEXT: fstod %f0, %f0
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; CHECK-NEXT: faddd %f0, %f2, %f0
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; CHECK-NEXT: restore
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define double @floatarg(double %a0, ; %i0,%i1
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float %a1, ; %i2
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double %a2, ; %i3, %i4
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double %a3, ; %i5, [%fp+92] (using 4 bytes)
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double %a4, ; [%fp+96] (using 8 bytes)
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float %a5) { ; [%fp+104] (using 4 bytes)
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%d1 = fpext float %a1 to double
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%s1 = fadd double %a0, %d1
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%s2 = fadd double %a2, %s1
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%s3 = fadd double %a3, %s2
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%s4 = fadd double %a4, %s3
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%d5 = fpext float %a5 to double
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%s5 = fadd double %d5, %s4
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ret double %s5
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}
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; CHECK-LABEL: call_floatarg:
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; CHECK: save %sp, -112, %sp
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; CHECK: mov %i2, %o1
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; CHECK-NEXT: mov %i1, %o0
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; CHECK-NEXT: st %i0, [%sp+104]
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; CHECK-NEXT: std %o0, [%sp+96]
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; CHECK-NEXT: st %o1, [%sp+92]
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; CHECK-NEXT: mov %i0, %o2
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; CHECK-NEXT: mov %o0, %o3
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; CHECK-NEXT: mov %o1, %o4
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; CHECK-NEXT: mov %o0, %o5
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; CHECK-NEXT: call floatarg
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; CHECK: std %f0, [%i4]
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; CHECK: restore
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define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
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%r = call double @floatarg(double %d2, float %f1, double %d2, double %d2,
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double %d2, float %f1)
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store double %r, double* %p
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ret void
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}
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;; i64 arguments should effectively work the same as double: split
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;; into two locations. This is different for little-endian vs big
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;; endian, since the 64-bit math needs to be split
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; CHECK-LABEL: i64arg:
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; CHECK: save %sp, -96, %sp
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; CHECK-BE: ld [%fp+100], %g2
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; CHECK-BE-NEXT: ld [%fp+96], %g3
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; CHECK-BE-NEXT: ld [%fp+92], %g4
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; CHECK-BE-NEXT: addcc %i1, %i2, %i1
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; CHECK-BE-NEXT: addxcc %i0, 0, %i0
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; CHECK-BE-NEXT: addcc %i4, %i1, %i1
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; CHECK-BE-NEXT: addxcc %i3, %i0, %i0
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; CHECK-BE-NEXT: addcc %g4, %i1, %i1
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; CHECK-BE-NEXT: ld [%fp+104], %i2
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; CHECK-BE-NEXT: addxcc %i5, %i0, %i0
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; CHECK-BE-NEXT: addcc %g2, %i1, %i1
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; CHECK-BE-NEXT: addxcc %g3, %i0, %i0
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; CHECK-BE-NEXT: addcc %i2, %i1, %i1
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; CHECK-BE-NEXT: addxcc %i0, 0, %i0
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;
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; CHECK-LE: ld [%fp+96], %g2
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; CHECK-LE-NEXT: ld [%fp+100], %g3
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; CHECK-LE-NEXT: ld [%fp+92], %g4
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; CHECK-LE-NEXT: addcc %i0, %i2, %i0
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; CHECK-LE-NEXT: addxcc %i1, 0, %i1
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; CHECK-LE-NEXT: addcc %i3, %i0, %i0
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; CHECK-LE-NEXT: addxcc %i4, %i1, %i1
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; CHECK-LE-NEXT: addcc %i5, %i0, %i0
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; CHECK-LE-NEXT: ld [%fp+104], %i2
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; CHECK-LE-NEXT: addxcc %g4, %i1, %i1
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; CHECK-LE-NEXT: addcc %g2, %i0, %i0
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; CHECK-LE-NEXT: addxcc %g3, %i1, %i1
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; CHECK-LE-NEXT: addcc %i2, %i0, %i0
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; CHECK-LE-NEXT: addxcc %i1, 0, %i1
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; CHECK-NEXT: restore
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define i64 @i64arg(i64 %a0, ; %i0,%i1
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i32 %a1, ; %i2
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i64 %a2, ; %i3, %i4
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i64 %a3, ; %i5, [%fp+92] (using 4 bytes)
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i64 %a4, ; [%fp+96] (using 8 bytes)
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i32 %a5) { ; [%fp+104] (using 4 bytes)
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%a1L = zext i32 %a1 to i64
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%s1 = add i64 %a0, %a1L
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%s2 = add i64 %a2, %s1
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%s3 = add i64 %a3, %s2
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%s4 = add i64 %a4, %s3
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%a5L = zext i32 %a5 to i64
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%s5 = add i64 %a5L, %s4
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ret i64 %s5
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}
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; CHECK-LABEL: call_i64arg:
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; CHECK: save %sp, -112, %sp
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; CHECK: st %i0, [%sp+104]
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; CHECK-NEXT: st %i2, [%sp+100]
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; CHECK-NEXT: st %i1, [%sp+96]
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; CHECK-NEXT: st %i2, [%sp+92]
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; CHECK-NEXT: mov %i1, %o0
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; CHECK-NEXT: mov %i2, %o1
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; CHECK-NEXT: mov %i0, %o2
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; CHECK-NEXT: mov %i1, %o3
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; CHECK-NEXT: mov %i2, %o4
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; CHECK-NEXT: mov %i1, %o5
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; CHECK-NEXT: call i64arg
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; CHECK: std %o0, [%i3]
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; CHECK-NEXT: restore
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define void @call_i64arg(i32 %a0, i64 %a1, i64* %p) {
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%r = call i64 @i64arg(i64 %a1, i32 %a0, i64 %a1, i64 %a1, i64 %a1, i32 %a0)
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store i64 %r, i64* %p
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ret void
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}
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