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Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
565bdbf598
commit
ac81cc3282
@ -368,9 +368,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(NegFrameSize);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
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.addReg(PPC::R1, RegState::Kill)
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.addReg(PPC::R1, RegState::Define)
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.addReg(PPC::R1)
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.addReg(PPC::R0);
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} else if (isInt<16>(NegFrameSize)) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
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@ -383,9 +383,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
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.addReg(PPC::R0, RegState::Kill)
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.addImm(NegFrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
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.addReg(PPC::R1, RegState::Kill)
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.addReg(PPC::R1, RegState::Define)
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.addReg(PPC::R1)
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.addReg(PPC::R0);
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}
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} else { // PPC64.
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@ -401,9 +401,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
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.addReg(PPC::X0)
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.addImm(NegFrameSize);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
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.addReg(PPC::X1, RegState::Kill)
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.addReg(PPC::X1, RegState::Define)
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.addReg(PPC::X1)
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.addReg(PPC::X0);
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} else if (isInt<16>(NegFrameSize)) {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
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@ -416,9 +416,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
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.addReg(PPC::X0, RegState::Kill)
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.addImm(NegFrameSize & 0xFFFF);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
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.addReg(PPC::X1, RegState::Kill)
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.addReg(PPC::X1, RegState::Define)
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.addReg(PPC::X1)
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.addReg(PPC::X0);
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}
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}
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@ -111,6 +111,18 @@ namespace {
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/// immediate field. Because preinc imms have already been validated, just
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/// accept it.
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bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
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if (isa<ConstantSDNode>(N)) {
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Out = N;
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return true;
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}
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return false;
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}
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/// SelectAddrIdxOffs - Return true if the operand is valid for a preinc
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/// index field. Because preinc imms have already been validated, just
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/// accept it.
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bool SelectAddrIdxOffs(SDValue N, SDValue &Out) const {
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Out = N;
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return true;
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}
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@ -1105,7 +1105,15 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
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if (VT.isVector())
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return false;
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// TODO: Check reg+reg first.
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if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
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if (isa<StoreSDNode>(N)) {
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AM = ISD::PRE_INC;
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return true;
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}
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// FIXME: reg+reg preinc loads
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return false;
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}
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// LDU/STU use reg+imm*4, others use reg+imm.
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if (VT != MVT::i64) {
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@ -680,10 +680,41 @@ def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
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RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
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isPPC64;
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let mayStore = 1 in
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def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
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"stdux $rS, $dst", LdStSTD,
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[]>, isPPC64;
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def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stbux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_truncsti8 G8RC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"sthux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_truncsti16 G8RC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stwux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_truncsti32 G8RC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res),
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(ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stdux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked, isPPC64;
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// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
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def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
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@ -349,6 +349,7 @@ def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
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/// This is just the offset part of iaddr, used for preinc.
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def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
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def xaddroff : ComplexPattern<iPTR, 1, "SelectAddrIdxOffs", [], []>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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@ -822,12 +823,49 @@ def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
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"stwx $rS, $dst", LdStStore,
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[(store GPRC:$rS, xaddr:$dst)]>,
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PPC970_DGroup_Cracked;
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let mayStore = 1 in {
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def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
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"stwux $rS, $rA, $rB", LdStStore,
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[]>;
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}
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def STBUX : XForm_8<31, 247, (outs ptr_rc:$ea_res),
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(ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stbux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_truncsti8 GPRC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STHUX : XForm_8<31, 439, (outs ptr_rc:$ea_res),
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(ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"sthux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_truncsti16 GPRC:$rS,
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ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STWUX : XForm_8<31, 183, (outs ptr_rc:$ea_res),
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(ins GPRC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stwux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_store GPRC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STFSUX : XForm_8<31, 695, (outs ptr_rc:$ea_res),
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(ins F4RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stfsux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_store F4RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STFDUX : XForm_8<31, 759, (outs ptr_rc:$ea_res),
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(ins F8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg),
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"stfdux $rS, $ptroff, $ptrreg", LdStStore,
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[(set ptr_rc:$ea_res,
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(pre_store F8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>,
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RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">,
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PPC970_DGroup_Cracked;
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def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
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"sthbrx $rS, $dst", LdStStore,
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[(PPCstbrx GPRC:$rS, xoaddr:$dst, i16)]>,
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@ -328,14 +328,14 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
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// address of new allocated space.
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if (LP64) {
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if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
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.addReg(Reg, RegState::Kill)
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.addReg(PPC::X1, RegState::Define)
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.addReg(PPC::X1)
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.addReg(MI.getOperand(1).getReg());
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else
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
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BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
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.addReg(PPC::X0, RegState::Kill)
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.addReg(PPC::X1, RegState::Define)
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.addReg(PPC::X1)
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.addReg(MI.getOperand(1).getReg());
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if (!MI.getOperand(1).isKill())
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@ -349,9 +349,9 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
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.addImm(maxCallFrameSize)
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.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
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} else {
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BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
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BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
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.addReg(Reg, RegState::Kill)
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.addReg(PPC::R1, RegState::Define)
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.addReg(PPC::R1)
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.addReg(MI.getOperand(1).getReg());
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if (!MI.getOperand(1).isKill())
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47
test/CodeGen/PowerPC/stwux.ll
Normal file
47
test/CodeGen/PowerPC/stwux.ll
Normal file
@ -0,0 +1,47 @@
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; RUN: llc < %s | FileCheck %s
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@multvec_i = external unnamed_addr global [100 x i32], align 4
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define fastcc void @subs_STMultiExceptIntern() nounwind {
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entry:
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br i1 undef, label %while.body.lr.ph, label %return
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while.body.lr.ph: ; preds = %entry
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br label %while.body
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while.body: ; preds = %if.end12, %while.body.lr.ph
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%i.0240 = phi i32 [ -1, %while.body.lr.ph ], [ %i.1, %if.end12 ]
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br i1 undef, label %if.end12, label %if.then
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if.then: ; preds = %while.body
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br label %if.end12
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if.end12: ; preds = %if.then, %while.body
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%i.1 = phi i32 [ %i.0240, %while.body ], [ undef, %if.then ]
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br i1 undef, label %while.body, label %while.end
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while.end: ; preds = %if.end12
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br i1 undef, label %return, label %if.end15
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if.end15: ; preds = %while.end
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%idxprom.i.i230 = sext i32 %i.1 to i64
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%arrayidx18 = getelementptr inbounds [100 x i32]* @multvec_i, i64 0, i64 %idxprom.i.i230
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store i32 0, i32* %arrayidx18, align 4
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br i1 undef, label %while.body21, label %while.end90
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while.body21: ; preds = %if.end15
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unreachable
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while.end90: ; preds = %if.end15
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store i32 0, i32* %arrayidx18, align 4
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br label %return
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return: ; preds = %while.end90, %while.end, %entry
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ret void
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; CHECK: @subs_STMultiExceptIntern
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; CHECK: stwux
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}
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