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Add intrinsics for sin, cos, and pow. These use llvm_anyfloat_ty, and so

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may be overloaded with vector types. And add a testcase for codegen for
these.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2007-10-12 00:01:22 +00:00
parent 8266952813
commit ac9385a555
3 changed files with 47 additions and 0 deletions
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4
include/llvm/Intrinsics.td
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@ -184,6 +184,10 @@ let Properties = [IntrWriteArgMem] in {
let Properties = [IntrNoMem] in { let Properties = [IntrNoMem] in {
def int_sqrt : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>; def int_sqrt : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
def int_powi : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>, llvm_i32_ty]>; def int_powi : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>, llvm_i32_ty]>;
def int_sin : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
def int_cos : Intrinsic<[llvm_anyfloat_ty, LLVMMatchType<0>]>;
def int_pow : Intrinsic<[llvm_anyfloat_ty,
LLVMMatchType<0>, LLVMMatchType<0>]>;
} }
// NOTE: these are internal interfaces. // NOTE: these are internal interfaces.

16
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -2807,6 +2807,22 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
getValue(I.getOperand(1)), getValue(I.getOperand(1)),
getValue(I.getOperand(2)))); getValue(I.getOperand(2))));
return 0; return 0;
case Intrinsic::sin:
setValue(&I, DAG.getNode(ISD::FSIN,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::cos:
setValue(&I, DAG.getNode(ISD::FCOS,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
case Intrinsic::pow:
setValue(&I, DAG.getNode(ISD::FPOW,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
return 0;
case Intrinsic::pcmarker: { case Intrinsic::pcmarker: {
SDOperand Tmp = getValue(I.getOperand(1)); SDOperand Tmp = getValue(I.getOperand(1));
DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp)); DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));

27
test/CodeGen/X86/vector-intrinsics.ll Normal file
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@ -0,0 +1,27 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep call | count 16
declare <4 x double> @llvm.sin.v4f64(<4 x double> %p)
declare <4 x double> @llvm.cos.v4f64(<4 x double> %p)
declare <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
declare <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32)
define <4 x double> @foo(<4 x double> %p)
{
%t = call <4 x double> @llvm.sin.v4f64(<4 x double> %p)
ret <4 x double> %t
}
define <4 x double> @goo(<4 x double> %p)
{
%t = call <4 x double> @llvm.cos.v4f64(<4 x double> %p)
ret <4 x double> %t
}
define <4 x double> @moo(<4 x double> %p, <4 x double> %q)
{
%t = call <4 x double> @llvm.pow.v4f64(<4 x double> %p, <4 x double> %q)
ret <4 x double> %t
}
define <4 x double> @zoo(<4 x double> %p, i32 %q)
{
%t = call <4 x double> @llvm.powi.v4f64(<4 x double> %p, i32 %q)
ret <4 x double> %t
}