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[TargetLowering] use isSubsetOf in SimplifyDemandedBits; NFCI

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This is the DAG equivalent of https://reviews.llvm.org/D32255 , 
which will hopefully be committed again. The functionality
(preferring a 'not' op) is already here in the DAG, so this is
just intended to be a clean-up and performance improvement.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302087 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sanjay Patel 2017-05-03 21:55:34 +00:00
parent 2dbf23f50c
commit acf74d2493
1 changed files with 14 additions and 18 deletions
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32
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -659,7 +659,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// Output known-1 are known to be set if set in either the LHS | RHS. // Output known-1 are known to be set if set in either the LHS | RHS.
Known.One |= Known2.One; Known.One |= Known2.One;
break; break;
case ISD::XOR: case ISD::XOR: {
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1)) if (SimplifyDemandedBits(Op.getOperand(1), NewMask, Known, TLO, Depth+1))
return true; return true;
assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?"); assert((Known.Zero & Known.One) == 0 && "Bits known to be one AND zero?");
@ -704,28 +704,24 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
} }
} }
// If the RHS is a constant, see if we can simplify it. // If the RHS is a constant, see if we can change it. Don't alter a -1
// for XOR, we prefer to force bits to 1 if they will make a -1. // constant because that's a 'not' op, and that is better for combining and
// If we can't force bits, try to shrink the constant. // codegen.
if (ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1))) { ConstantSDNode *C = isConstOrConstSplat(Op.getOperand(1));
APInt Expanded = C->getAPIntValue() | (~NewMask); if (C && !C->isAllOnesValue()) {
// If we can expand it to have all bits set, do it. if (NewMask.isSubsetOf(C->getAPIntValue())) {
if (Expanded.isAllOnesValue()) { // We're flipping all demanded bits. Flip the undemanded bits too.
if (Expanded != C->getAPIntValue()) { SDValue New = TLO.DAG.getNOT(dl, Op.getOperand(0), Op.getValueType());
EVT VT = Op.getValueType(); return TLO.CombineTo(Op, New);
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, dl, VT));
return TLO.CombineTo(Op, New);
}
// If it already has all the bits set, nothing to change
// but don't shrink either!
} else if (ShrinkDemandedConstant(Op, NewMask, TLO)) {
return true;
} }
// If we can't turn this into a 'not', try to shrink the constant.
if (ShrinkDemandedConstant(Op, NewMask, TLO))
return true;
} }
Known = std::move(KnownOut); Known = std::move(KnownOut);
break; break;
}
case ISD::SELECT: case ISD::SELECT:
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, Known, TLO, Depth+1)) if (SimplifyDemandedBits(Op.getOperand(2), NewMask, Known, TLO, Depth+1))
return true; return true;