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Add another accidentally omitted predicate operand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-08-11 22:08:38 +00:00
parent 1fb6673bc2
commit adf2b094cb
1 changed files with 2 additions and 0 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2491,6 +2491,7 @@ static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
unsigned pred = fieldFromInstruction32(Insn, 28, 4);
if (Inst.getOpcode() == ARM::STREXD)
if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
@ -2501,6 +2502,7 @@ static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
return true;
}