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https://github.com/RPCSX/llvm.git
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Corrected reodering code for instructions inserted before calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
parent
984adc25c9
commit
ae4bcd7566
@ -271,6 +271,22 @@ class UltraSparcRegInfo : public MachineRegInfo
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}
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int getRegType(int reg) const {
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if( reg < 32 )
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return IntRegType;
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else if ( reg < (32 + 32) )
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return FPSingleRegType;
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else if ( reg < (64 + 32) )
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return FPDoubleRegType;
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else if( reg < (64+32+4) )
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return FloatCCRegType;
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else if( reg < (64+32+4+2) )
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return IntCCRegType;
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else
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assert(0 && "Invalid register number in getRegType");
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}
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// ***TODO: See this method is necessary
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@ -284,8 +300,19 @@ class UltraSparcRegInfo : public MachineRegInfo
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MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
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MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
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void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst,
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PhyRegAlloc &PRA ) const;
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void OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
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vector<MachineInstr *> &OrdVec) const;
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vector<MachineInstr *> &OrdVec,
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PhyRegAlloc &PRA) const;
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public:
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@ -741,16 +741,16 @@ void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
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if( ! AddedInstrnsBefore.empty() ) {
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if( DEBUG_RA) {
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if( DEBUG_RA ) {
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cerr << "\nCalling reorder with instrns: \n";
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for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
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cerr << *(AddedInstrnsBefore[i]);
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}
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vector <MachineInstr *> TmpVec;
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OrderAddedInstrns(AddedInstrnsBefore, TmpVec);
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OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
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if( DEBUG_RA) {
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if( DEBUG_RA ) {
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cerr << "\nAfter reordering instrns: \n";
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for(unsigned i=0; i < TmpVec.size(); i++)
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cerr << *(TmpVec[i]);
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@ -1007,7 +1007,7 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
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MI->SetMachineOperand(0, SrcPtrReg, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperand(2, DestReg, false);
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MI->SetMachineOperand(2, DestReg, true);
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break;
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case FPSingleRegType:
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@ -1015,7 +1015,7 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
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MI->SetMachineOperand(0, SrcPtrReg, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperand(2, DestReg, false);
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MI->SetMachineOperand(2, DestReg, true);
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break;
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@ -1024,14 +1024,14 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
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MI->SetMachineOperand(0, SrcPtrReg, false);
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MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
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(int64_t) Offset, false);
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MI->SetMachineOperand(2, DestReg, false);
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MI->SetMachineOperand(2, DestReg, true);
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break;
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case IntCCRegType:
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assert( 0 && "Cannot directly load into %ccr from memory");
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default:
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assert(0 && "Unknow RegType in cpMem2RegMI");
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assert(0 && "Unknown RegType in cpMem2RegMI");
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}
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return MI;
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@ -1090,8 +1090,9 @@ void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
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LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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PushedRegSet.insert(
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getUnifiedRegNum((RetValLR->getRegClass())->getID(),
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if( RetValLR->hasColor())
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PushedRegSet.insert(
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getUnifiedRegNum((RetValLR->getRegClass())->getID(),
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RetValLR->getColor() ) );
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}
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@ -1312,17 +1313,24 @@ void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
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// they are used. If it detects such conditions, it reorders the instructions.
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//
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// The unordered instructions come in the UnordVec. These instructions are
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// instructions inserted by RegAlloc. All suhc instruction MUST have
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// their USES BEFORE THE DEFS.
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// instructions inserted by RegAlloc. All such instruction MUST have
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// their USES BEFORE THE DEFS after reordering.
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// The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
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// this method is called.
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// This method uses two vectors for efficiency in accessing
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// Since instructions are inserted in RegAlloc, this assumes that the
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// first operand is the source reg and the last operand is the dest reg.
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// All the uses are before THE def to a register
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//---------------------------------------------------------------------------
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void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
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vector<MachineInstr *> &OrdVec) const{
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vector<MachineInstr *> &OrdVec,
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PhyRegAlloc &PRA) const{
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/*
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Problem: We can have instructions inserted by RegAlloc like
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@ -1330,176 +1338,226 @@ void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
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2. add %oy %g0 %oz, where z!=x or z==x
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This is wrong since %oy used by 2 is overwritten by 1
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*/
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Solution:
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We re-order the instructions so that the uses are before the defs
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/* Algorithm:
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Round 1:
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For each instruction 'Inst' in UnordVec, starting from UnordVec.begin,
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let Def be the destination reg of instr.
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For each use 'Use' of the following instruction
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If Def==Use continue
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If no use is found, push back 'Inst' to OrdVec
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If no inst is left in UnordVec by the end of Round1, return
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Round 2:
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For each inst 'Inst' left in UnordVec
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For each use 'Use' in Inst
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If threre is NO Def for this Use in an inst in OrdVec
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push back Inst
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Else
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push_front a stack save instr mem location "Loc"
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push_back a restore inst to load to Use from Loc
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discard Inst (assert that one operand is %g0)
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Algorithm:
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do
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for each instruction 'DefInst' in the UnOrdVec
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for each instruction 'UseInst' that follows the DefInst
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if the reg defined by DefInst is used by UseInst
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mark DefInst as not movable in this iteration
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If DefInst is not marked as not-movable, move DefInst to OrdVec
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while all instructions in DefInst are moved to OrdVec
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For moving, we call the move2OrdVec(). It checks whether there is a def
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in it for the uses in the instruction to be added to OrdVec. If there
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are no preceding defs, it just appends the instruction. If there is a
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preceding def, it puts two instructions to save the reg on stack before
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the load and puts a restore at use.
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*/
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bool CouldMoveAll = true;
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bool CouldMoveAll;
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bool DebugPrint = false;
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vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
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do {
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for( ; DefIt != UnordVec.end(); ++DefIt ) {
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CouldMoveAll = true;
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// for each instruction in the UnordVec do ...
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vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
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MachineInstr *DefInst = *DefIt;
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for( ; DefIt != UnordVec.end(); ++DefIt ) {
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// cerr << "\nDefInst = " << *DefInst;
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// for each instruction in the UnordVec do ...
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for(unsigned OpNumD=0; OpNumD < DefInst->getNumOperands(); ++OpNumD) {
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MachineInstr *DefInst = *DefIt;
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MachineOperand& DefOp = DefInst->getOperand(OpNumD);
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if( DefInst == NULL) continue;
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//cerr << "\nInst in UnordVec = " << *DefInst;
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// last operand is the def (unless for a store which has no def reg)
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MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
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if( DefOp.opIsDef() &&
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DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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// If the operand in DefInst is a def ...
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bool DefEqUse = false;
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vector<MachineInstr *>::iterator UseIt = DefIt;
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UseIt++;
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for( ; UseIt != UnordVec.end(); ++UseIt ) {
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// for each inst (UseInst) that is below the DefInst do ...
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MachineInstr *UseInst = *UseIt;
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if( UseInst == NULL) continue;
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// for each inst (UseInst) that is below the DefInst do ...
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for(unsigned OpNumU=0; OpNumU < UseInst->getNumOperands(); ++OpNumU){
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MachineOperand& UseOp = UseInst->getOperand(OpNumU);
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if( ! UseOp.opIsDef() &&
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UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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// if use is a register ...
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if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
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// if Def and this use are the same, it means that this use
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// is destroyed by a def before it is used
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DefEqUse = true;
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CouldMoveAll = false;
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cerr << "\nReordered Ins (Moved up): " << *UseInst;
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break;
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} // if two registers are equal
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} // if use is a register
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} // for all uses
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MachineOperand& UseOp = UseInst->getOperand(0);
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if( ! UseOp.opIsDef() &&
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UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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// if use is a register ...
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if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
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// if Def and this use are the same, it means that this use
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// is destroyed by a def before it is used
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// cerr << "\nCouldn't move " << *DefInst;
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DefEqUse = true;
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CouldMoveAll = false;
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DebugPrint = true;
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break;
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} // if two registers are equal
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} // if use is a register
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}// for all use instructions
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if( ! DefEqUse ) {
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// cerr << "\nMoved Inst = " << *DefInst;
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OrdVec.push_back(DefInst);
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// after examining all the instructions that follow the DefInst
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// if there are no dependencies, we can move it to the OrdVec
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// cerr << "Moved to Ord: " << *DefInst;
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moveInst2OrdVec(OrdVec, DefInst, PRA);
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//OrdVec.push_back(DefInst);
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// mark the pos of DefInst with NULL to indicate that it is
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// empty
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*DefIt = NULL;
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}
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else
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break; // exit the loop since we can't move DefInst
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} // if Def is a machine register
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} // for all instructions in the UnordVec
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} // for all Defs in DefInst (there should be only 1)
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} // for all instructions in the UnordVec
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} while( !CouldMoveAll);
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if( CouldMoveAll ) {
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assert( (UnordVec.size() == OrdVec.size()) &&
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"Different Vec Sizes after reordering");
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return;
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if(DebugPrint) {
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cerr << "\nAdded instructions were reordered to:\n";
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for(unsigned int i=0; i < OrdVec.size(); i++)
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cerr << *(OrdVec[i]);
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}
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// We are here because there were two instructions like:
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// 1. add %ox %g0 %oy
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// 2. add %oy %g0 %oz, where z!=x or z==x
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// and hence we could not move 1 to the OrdVec
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// cerr << "\nCaution: Added instructions will be RE-ORDERED !@!@!";
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vector< MachineInstr *>::iterator UnordIt = UnordVec.begin();
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for( ; UnordIt != UnordVec.end(); ++UnordIt ) {
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MachineInstr *UnordInst = *UnordIt;
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if( UnordInst == NULL ) continue;
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for(unsigned OpNumU=0; OpNumU < UnordInst->getNumOperands(); ++OpNumU) {
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MachineOperand& UseOp = UnordInst->getOperand(OpNumU);
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if( ! UseOp.opIsDef() &&
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UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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if( UseOp.getMachineRegNum() == getZeroRegNum() )
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continue;
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// for all uses of UnordInst
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bool DefEqUse = false;
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vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
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for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
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MachineInstr *OrdInst = *OrdIt ;
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for(unsigned OpNumO=0; OpNumO < OrdInst->getNumOperands(); ++OpNumO){
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MachineOperand& DefOp = OrdInst->getOperand(OpNumO);
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if( DefOp.opIsDef() &&
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DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
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DefEqUse = true;
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assert(0 && "Insert save/restre code for reordering");
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} // if two registers are equal
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} // if Def is a register
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} // for all defs
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} // for each instr in OrdVec
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if( !DefEqUse ) {
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OrdVec.push_back( UnordInst );
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cerr << "\nReordered instr (Moved Down): " << *UnordInst;
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}
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} // if the operand in UnordInst is a use
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} // for each use in the UnordInst
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} // for each UnordInst in UnordVec
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}
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void UltraSparcRegInfo::moveInst2OrdVec(vector<MachineInstr *> &OrdVec,
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MachineInstr *UnordInst,
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PhyRegAlloc &PRA ) const {
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MachineOperand& UseOp = UnordInst->getOperand(0);
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if( ! UseOp.opIsDef() &&
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UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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// for the use of UnordInst, see whether there is a defining instr
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// before in the OrdVec
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bool DefEqUse = false;
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vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
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for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
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MachineInstr *OrdInst = *OrdIt ;
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MachineOperand& DefOp =
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OrdInst->getOperand(OrdInst->getNumOperands()-1);
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if( DefOp.opIsDef() &&
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DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
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//cerr << "\nDefining Ord Inst: " << *OrdInst;
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if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
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// we are here because there is a preceding def in the OrdVec
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// for the use in this intr we are going to insert. This
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// happened because the original code was like:
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// 1. add %ox %g0 %oy
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// 2. add %oy %g0 %ox
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// In Round1, we added 2 to OrdVec but 1 remained in UnordVec
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// Now we are processing %ox of 1.
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// We have to
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const int UReg = DefOp.getMachineRegNum();
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const int RegType = getRegType(UReg);
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MachineInstr *AdIBef, *AdIAft;
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// TODO: Change 8 below
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const int StackOff = PRA.mcInfo.pushTempValue(target, 8);
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// Save the UReg (%ox) on stack before it's destroyed
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AdIBef=cpReg2MemMI(UReg, getStackPointer(), StackOff, RegType);
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OrdIt = OrdVec.insert( OrdIt, AdIBef);
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OrdIt++; // points to current instr we processed
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// Load directly into DReg (%oy)
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MachineOperand& DOp=
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(UnordInst->getOperand(UnordInst->getNumOperands()-1));
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assert(DOp.opIsDef() && "Last operand is not the def");
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const int DReg = DOp.getMachineRegNum();
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AdIAft=cpMem2RegMI(getStackPointer(), StackOff, DReg, RegType);
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OrdVec.push_back(AdIAft);
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cerr << "\nFixed CIRCULAR references by reordering";
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if( DEBUG_RA ) {
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cerr << "\nBefore CIRCULAR Reordering:\n";
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cerr << *UnordInst;
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cerr << *OrdInst;
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cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
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for(unsigned i=0; i < OrdVec.size(); i++)
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cerr << *(OrdVec[i]);
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}
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// Do not copy the UseInst to OrdVec
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DefEqUse = true;
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break;
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}// if two registers are equal
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} // if Def is a register
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} // for each instr in OrdVec
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if( !DefEqUse ) {
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// We didn't find a def in the OrdVec, so just append this inst
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OrdVec.push_back( UnordInst );
|
||||
//cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
|
||||
}
|
||||
|
||||
}// if the operand in UnordInst is a use
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user