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Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs array in
CodeGenTarget.cpp to avoid the ordering dependence. NFCI. Differential Revision: http://reviews.llvm.org/D16826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@259726 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David L Kreitzer
parent
f38d8c901e
commit
af50aacb9a
153
include/llvm/Target/TargetOpcodes.def
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153
include/llvm/Target/TargetOpcodes.def
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//===-- llvm/Target/TargetOpcodes.def - Target Indep Opcodes ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target independent instruction opcodes.
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//
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//===----------------------------------------------------------------------===//
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// NOTE: NO INCLUDE GUARD DESIRED!
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/// HANDLE_TARGET_OPCODE defines an opcode and its associated enum value.
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///
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#ifndef HANDLE_TARGET_OPCODE
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#define HANDLE_TARGET_OPCODE(OPC, NUM)
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#endif
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/// HANDLE_TARGET_OPCODE_MARKER defines an alternative identifier for an opcode.
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///
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#ifndef HANDLE_TARGET_OPCODE_MARKER
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#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
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#endif
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/// Every instruction defined here must also appear in Target.td.
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///
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HANDLE_TARGET_OPCODE(PHI, 0)
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HANDLE_TARGET_OPCODE(INLINEASM, 1)
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HANDLE_TARGET_OPCODE(CFI_INSTRUCTION, 2)
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HANDLE_TARGET_OPCODE(EH_LABEL, 3)
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HANDLE_TARGET_OPCODE(GC_LABEL, 4)
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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HANDLE_TARGET_OPCODE(KILL, 5)
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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HANDLE_TARGET_OPCODE(EXTRACT_SUBREG, 6)
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/// INSERT_SUBREG - This instruction takes three operands: a register that
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/// has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with the
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/// value of the second register inserted. The first register is often
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/// defined by an IMPLICIT_DEF, because it is commonly used to implement
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/// anyext operations on target architectures which support it.
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HANDLE_TARGET_OPCODE(INSERT_SUBREG, 7)
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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HANDLE_TARGET_OPCODE(IMPLICIT_DEF, 8)
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
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/// the first operand is an immediate integer constant. This constant is
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/// often zero, because it is commonly used to assert that the instruction
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/// defining the register implicitly clears the high bits.
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HANDLE_TARGET_OPCODE(SUBREG_TO_REG, 9)
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. It is emitted as a COPY MachineInstr.
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HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS, 10)
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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HANDLE_TARGET_OPCODE(DBG_VALUE, 11)
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represents a consecutive sequence of sub-registers. It's used as a
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/// register coalescing / allocation aid and must be eliminated before code
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/// emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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HANDLE_TARGET_OPCODE(REG_SEQUENCE, 12)
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/// COPY - Target-independent register copy. This instruction can also be
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/// used to copy between subregisters of virtual registers.
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HANDLE_TARGET_OPCODE(COPY, 13)
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/// BUNDLE - This instruction represents an instruction bundle. Instructions
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/// which immediately follow a BUNDLE instruction which are marked with
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/// 'InsideBundle' flag are inside the bundle.
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HANDLE_TARGET_OPCODE(BUNDLE, 14)
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/// Lifetime markers.
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HANDLE_TARGET_OPCODE(LIFETIME_START, 15)
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HANDLE_TARGET_OPCODE(LIFETIME_END, 16)
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/// A Stackmap instruction captures the location of live variables at its
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/// position in the instruction stream. It is followed by a shadow of bytes
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/// that must lie within the function and not contain another stackmap.
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HANDLE_TARGET_OPCODE(STACKMAP, 17)
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/// Patchable call instruction - this instruction represents a call to a
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/// constant address, followed by a series of NOPs. It is intended to
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/// support optimizations for dynamic languages (such as javascript) that
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/// rewrite calls to runtimes with more efficient code sequences.
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/// This also implies a stack map.
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HANDLE_TARGET_OPCODE(PATCHPOINT, 18)
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/// This pseudo-instruction loads the stack guard value. Targets which need
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/// to prevent the stack guard value or address from being spilled to the
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/// stack should override TargetLowering::emitLoadStackGuardNode and
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/// additionally expand this pseudo after register allocation.
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HANDLE_TARGET_OPCODE(LOAD_STACK_GUARD, 19)
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/// Call instruction with associated vm state for deoptimization and list
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/// of live pointers for relocation by the garbage collector. It is
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/// intended to support garbage collection with fully precise relocating
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/// collectors and deoptimizations in either the callee or caller.
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HANDLE_TARGET_OPCODE(STATEPOINT, 20)
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/// Instruction that records the offset of a local stack allocation passed to
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/// llvm.localescape. It has two arguments: the symbol for the label and the
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/// frame index of the local stack allocation.
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HANDLE_TARGET_OPCODE(LOCAL_ESCAPE, 21)
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/// Loading instruction that may page fault, bundled with associated
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/// information on how to handle such a page fault. It is intended to support
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/// "zero cost" null checks in managed languages by allowing LLVM to fold
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/// comparisons into existing memory operations.
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HANDLE_TARGET_OPCODE(FAULTING_LOAD_OP, 22)
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/// The following generic opcodes are not supposed to appear after ISel.
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/// This is something we might want to relax, but for now, this is convenient
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/// to produce diagnostics.
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/// Generic ADD instruction. This is an integer add.
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HANDLE_TARGET_OPCODE(G_ADD, 23)
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
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// TODO: Add more generic opcodes as we move along.
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/// Marker for the end of the generic opcode.
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/// This is used to check if an opcode is in the range of the
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/// generic opcodes.
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_ADD)
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/// BUILTIN_OP_END - This must be the last enum value in this list.
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/// The target-specific post-isel opcode values start here.
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HANDLE_TARGET_OPCODE_MARKER(GENERIC_OP_END, PRE_ISEL_GENERIC_OPCODE_END)
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@ -18,138 +18,11 @@ namespace llvm {
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/// Invariant opcodes: All instruction sets have these as their low opcodes.
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///
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/// Every instruction defined here must also appear in Target.td and the order
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/// must be the same as in CodeGenTarget.cpp.
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///
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namespace TargetOpcode {
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enum {
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PHI = 0,
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INLINEASM = 1,
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CFI_INSTRUCTION = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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KILL = 5,
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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EXTRACT_SUBREG = 6,
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/// INSERT_SUBREG - This instruction takes three operands: a register that
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/// has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with the
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/// value of the second register inserted. The first register is often
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/// defined by an IMPLICIT_DEF, because it is commonly used to implement
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/// anyext operations on target architectures which support it.
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INSERT_SUBREG = 7,
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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IMPLICIT_DEF = 8,
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
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/// the first operand is an immediate integer constant. This constant is
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/// often zero, because it is commonly used to assert that the instruction
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/// defining the register implicitly clears the high bits.
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SUBREG_TO_REG = 9,
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. It is emitted as a COPY MachineInstr.
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COPY_TO_REGCLASS = 10,
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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DBG_VALUE = 11,
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represents a consecutive sequence of sub-registers. It's used as a
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/// register coalescing / allocation aid and must be eliminated before code
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/// emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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REG_SEQUENCE = 12,
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/// COPY - Target-independent register copy. This instruction can also be
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/// used to copy between subregisters of virtual registers.
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COPY = 13,
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/// BUNDLE - This instruction represents an instruction bundle. Instructions
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/// which immediately follow a BUNDLE instruction which are marked with
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/// 'InsideBundle' flag are inside the bundle.
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BUNDLE = 14,
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/// Lifetime markers.
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LIFETIME_START = 15,
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LIFETIME_END = 16,
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/// A Stackmap instruction captures the location of live variables at its
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/// position in the instruction stream. It is followed by a shadow of bytes
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/// that must lie within the function and not contain another stackmap.
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STACKMAP = 17,
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/// Patchable call instruction - this instruction represents a call to a
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/// constant address, followed by a series of NOPs. It is intended to
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/// support optimizations for dynamic languages (such as javascript) that
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/// rewrite calls to runtimes with more efficient code sequences.
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/// This also implies a stack map.
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PATCHPOINT = 18,
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/// This pseudo-instruction loads the stack guard value. Targets which need
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/// to prevent the stack guard value or address from being spilled to the
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/// stack should override TargetLowering::emitLoadStackGuardNode and
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/// additionally expand this pseudo after register allocation.
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LOAD_STACK_GUARD = 19,
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/// Call instruction with associated vm state for deoptimization and list
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/// of live pointers for relocation by the garbage collector. It is
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/// intended to support garbage collection with fully precise relocating
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/// collectors and deoptimizations in either the callee or caller.
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STATEPOINT = 20,
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/// Instruction that records the offset of a local stack allocation passed to
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/// llvm.localescape. It has two arguments: the symbol for the label and the
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/// frame index of the local stack allocation.
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LOCAL_ESCAPE = 21,
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/// Loading instruction that may page fault, bundled with associated
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/// information on how to handle such a page fault. It is intended to support
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/// "zero cost" null checks in managed languages by allowing LLVM to fold
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/// comparisons into existing memory operations.
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FAULTING_LOAD_OP = 22,
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/// The following generic opcodes are not supposed to appear after ISel.
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/// This is something we might want to relax, but for now, this is convenient
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/// to produce diagnostic.
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PRE_ISEL_GENERIC_OPCODE_START,
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// Generic opcodes used before ISel are here.
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/// Generic ADD instruction. This is an integer add.
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G_ADD = PRE_ISEL_GENERIC_OPCODE_START,
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// TODO: Add more generic opcodes as we move along.
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// FIXME: Right now, we have to manually add any new opcode in
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// CodeGenTarget.cpp for TableGen to pick them up.
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// Moreover the order must match.
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/// Marker for the end of the generic opcode.
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/// This is used to check if an opcode is in the range of the
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/// generic opcodes.
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PRE_ISEL_GENERIC_OPCODE_END,
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/// BUILTIN_OP_END - This must be the last enum value in this list.
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/// The target-specific post-isel opcode values start here.
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GENERIC_OP_END = PRE_ISEL_GENERIC_OPCODE_END,
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#define HANDLE_TARGET_OPCODE(OPC, NUM) OPC = NUM,
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#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC,
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#include "llvm/Target/TargetOpcodes.def"
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};
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} // end namespace TargetOpcode
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} // end namespace llvm
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@ -300,19 +300,9 @@ GetInstByName(const char *Name,
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/// \brief Return all of the instructions defined by the target, ordered by
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/// their enum value.
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void CodeGenTarget::ComputeInstrsByEnum() const {
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// The ordering here must match the ordering in TargetOpcodes.h.
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// FIXME: It would be nice to have the opcode directly extracted
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// to avoid potential errors. At the very, least a compile time
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// error would be appreciated if the order does not match.
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static const char *const FixedInstrs[] = {
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"PHI", "INLINEASM", "CFI_INSTRUCTION", "EH_LABEL",
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"GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
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"IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
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"REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
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"LIFETIME_END", "STACKMAP", "PATCHPOINT", "LOAD_STACK_GUARD",
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"STATEPOINT", "LOCAL_ESCAPE", "FAULTING_LOAD_OP",
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// Generic opcodes for GlobalISel start here.
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"G_ADD",
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#define HANDLE_TARGET_OPCODE(OPC, NUM) #OPC,
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#include "llvm/Target/TargetOpcodes.def"
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nullptr};
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const auto &Insts = getInstructions();
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for (const char *const *p = FixedInstrs; *p; ++p) {
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