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[FastISel][AArch64] Also allow folding of sign-/zero-extend and shift-left for booleans (i1).

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Shift-left immediate with sign-/zero-extensions also works for boolean values.
Update the assert and the test cases to reflect that fact.

This should fix a bug found by Chad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-09-22 21:08:53 +00:00
parent e6f6980d5b
commit af989653e0
2 changed files with 51 additions and 2 deletions
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5
lib/Target/AArch64/AArch64FastISel.cpp
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@ -3453,8 +3453,9 @@ unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
bool IsZext) {
assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
"Unexpected source/return type pair.");
assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
SrcVT == MVT::i64) && "Unexpected source value type.");
assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
"Unexpected source value type.");
assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
RetVT == MVT::i64) && "Unexpected return value type.");

48
test/CodeGen/AArch64/fast-isel-shift.ll
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@ -1,5 +1,53 @@
; RUN: llc -fast-isel -fast-isel-abort -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: lsl_zext_i1_i16
; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define zeroext i16 @lsl_zext_i1_i16(i1 %b) {
%1 = zext i1 %b to i16
%2 = shl i16 %1, 4
ret i16 %2
}
; CHECK-LABEL: lsl_sext_i1_i16
; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define signext i16 @lsl_sext_i1_i16(i1 %b) {
%1 = sext i1 %b to i16
%2 = shl i16 %1, 4
ret i16 %2
}
; CHECK-LABEL: lsl_zext_i1_i32
; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define i32 @lsl_zext_i1_i32(i1 %b) {
%1 = zext i1 %b to i32
%2 = shl i32 %1, 4
ret i32 %2
}
; CHECK-LABEL: lsl_sext_i1_i32
; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define i32 @lsl_sext_i1_i32(i1 %b) {
%1 = sext i1 %b to i32
%2 = shl i32 %1, 4
ret i32 %2
}
; CHECK-LABEL: lsl_zext_i1_i64
; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
define i64 @lsl_zext_i1_i64(i1 %b) {
%1 = zext i1 %b to i64
%2 = shl i64 %1, 4
ret i64 %2
}
; CHECK-LABEL: lsl_sext_i1_i64
; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
define i64 @lsl_sext_i1_i64(i1 %b) {
%1 = sext i1 %b to i64
%2 = shl i64 %1, 4
ret i64 %2
}
; CHECK-LABEL: lslv_i8
; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]