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Fix more places which should be checking for iOS, not darwin.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2012-01-04 01:55:04 +00:00
parent 56f582d664
commit afad0fe59a
18 changed files with 36 additions and 36 deletions
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14
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -35,7 +35,7 @@ namespace ARMRI {
/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
/// or a stack/pc register that we should push/pop.
static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
using namespace ARM;
switch (Reg) {
case R0: case R1: case R2: case R3:
@ -43,25 +43,25 @@ static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
case LR: case SP: case PC:
return true;
case R8: case R9: case R10: case R11:
// For darwin we want r7 and lr to be next to each other.
return !isDarwin;
// For iOS we want r7 and lr to be next to each other.
return !isIOS;
default:
return false;
}
}
static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
using namespace ARM;
switch (Reg) {
case R8: case R9: case R10: case R11:
// Darwin has this second area.
return isDarwin;
// iOS has this second area.
return isIOS;
default:
return false;
}
}
static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
using namespace ARM;
switch (Reg) {
case D15: case D14: case D13: case D12:

20
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -41,8 +41,8 @@ skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
bool ARMFrameLowering::hasFP(const MachineFunction &MF) const {
const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
// Mac OS X requires FP not to be clobbered for backtracing purpose.
if (STI.isTargetDarwin())
// iOS requires FP not to be clobbered for backtracing purpose.
if (STI.isTargetIOS())
return true;
const MachineFrameInfo *MFI = MF.getFrameInfo();
@ -183,7 +183,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
case ARM::R11:
if (Reg == FramePtr)
FramePtrSpillFI = FI;
if (STI.isTargetDarwin()) {
if (STI.isTargetIOS()) {
AFI->addGPRCalleeSavedArea2Frame(FI);
GPRCS2Size += 4;
} else {
@ -206,8 +206,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
if (GPRCS1Size > 0) MBBI++;
// Set FP to point to the stack slot that contains the previous FP.
// For Darwin, FP is R7, which has now been stored in spill area 1.
// Otherwise, if this is not Darwin, all the callee-saved registers go
// For iOS, FP is R7, which has now been stored in spill area 1.
// Otherwise, if this is not iOS, all the callee-saved registers go
// into spill area 1, including the FP in R11. In either case, it is
// now safe to emit this assignment.
bool HasFP = hasFP(MF);
@ -383,7 +383,7 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
ARMCC::AL, 0, TII);
else {
// It's not possible to restore SP from FP in a single instruction.
// For Darwin, this looks like:
// For iOS, this looks like:
// mov sp, r7
// sub sp, #24
// This is bad, if an interrupt is taken after the mov, sp is in an
@ -583,7 +583,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
unsigned LastReg = 0;
for (; i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
if (!(Func)(Reg, STI.isTargetDarwin())) continue;
if (!(Func)(Reg, STI.isTargetIOS())) continue;
// D-registers in the aligned area DPRCS2 are NOT spilled here.
if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
@ -656,7 +656,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
bool DeleteRet = false;
for (; i != 0; --i) {
unsigned Reg = CSI[i-1].getReg();
if (!(Func)(Reg, STI.isTargetDarwin())) continue;
if (!(Func)(Reg, STI.isTargetIOS())) continue;
// The aligned reloads from area DPRCS2 are not inserted here.
if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
@ -1256,7 +1256,7 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (Spilled) {
NumGPRSpills++;
if (!STI.isTargetDarwin()) {
if (!STI.isTargetIOS()) {
if (Reg == ARM::LR)
LRSpilled = true;
CS1Spilled = true;
@ -1276,7 +1276,7 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
break;
}
} else {
if (!STI.isTargetDarwin()) {
if (!STI.isTargetIOS()) {
UnspilledCS1GPRs.push_back(Reg);
continue;
}

2
lib/Target/ARM/Thumb1FrameLowering.cpp
View File

@ -101,7 +101,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
case ARM::R11:
if (Reg == FramePtr)
FramePtrSpillFI = FI;
if (STI.isTargetDarwin()) {
if (STI.isTargetIOS()) {
AFI->addGPRCalleeSavedArea2Frame(FI);
GPRCS2Size += 4;
} else {

2
test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6,+vfp2 | FileCheck %s
@quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]

2
test/CodeGen/ARM/2010-12-07-PEIBug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -mcpu=cortex-a8 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s
; rdar://8728956
define hidden void @foo() nounwind ssp {

2
test/CodeGen/ARM/2011-08-25-ldmia_ret.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s
; Test that ldmia_ret preserves implicit operands for return values.
;
; This CFG is reduced from a benchmark miscompile. With current

8
test/CodeGen/ARM/arm-returnaddr.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios -regalloc=basic | FileCheck %s
; RUN: llc < %s -mtriple=thumbv6-apple-ios -regalloc=basic | FileCheck %s
; rdar://8015977
; rdar://8020118

2
test/CodeGen/ARM/debug-info-arg.ll
View File

@ -2,7 +2,7 @@
; Test to check argument y's debug info uses FI
; Radar 10048772
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-macosx10.7.0"
target triple = "thumbv7-apple-ios"
%struct.tag_s = type { i32, i32, i32 }

2
test/CodeGen/ARM/hello.ll
View File

@ -2,7 +2,7 @@
; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1
; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \
; RUN: grep mov | count 2
; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2
; RUN: llc < %s -mtriple=armv6-apple-ios | grep mov | count 2
@str = internal constant [12 x i8] c"Hello World\00"

2
test/CodeGen/ARM/ifcvt10.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a9 | FileCheck %s
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a9 | FileCheck %s
; rdar://8402126
; Make sure if-converter is not predicating vldmia and ldmia. These are
; micro-coded and would have long issue latency even if predicated on

2
test/CodeGen/ARM/ifcvt5.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
@x = external global i32* ; <i32**> [#uses=1]

2
test/CodeGen/ARM/ifcvt6.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
define void @foo(i32 %X, i32 %Y) {
entry:

2
test/CodeGen/ARM/insn-sched1.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=arm -mattr=+v6
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 |\
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+v6 |\
; RUN: grep mov | count 3
define i32 @test(i32 %x) {

2
test/CodeGen/ARM/lsr-unfolded-offset.ll
View File

@ -12,7 +12,7 @@
; CHECK: add
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
target triple = "thumbv7-apple-macosx10.7.0"
target triple = "thumbv7-apple-ios"
%struct.partition_entry = type { i32, i32, i64, i64 }

2
test/CodeGen/Thumb/large-stack.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s
define void @test1() {
; CHECK: test1:

2
test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
View File

@ -1,5 +1,5 @@
; rdar://8465407
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
%struct.buf = type opaque

2
test/CodeGen/Thumb2/thumb2-ifcvt2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s
define void @foo(i32 %X, i32 %Y) {
entry:

2
test/CodeGen/Thumb2/thumb2-ldm.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mattr=+thumb2 | FileCheck %s
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]