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Introduce target hook for optimizing register copies
Allow a target to do something other than search for copies that will avoid cross register bank copies. Implement for SI by only rewriting the most basic copies, so it should look through anything like a subregister extract. I'm not entirely satisified with this because it seems like eliminating a reg_sequence that isn't fully used should work generically for all targets without them having to override something. However, it seems to be tricky to have a simple implementation of this without rewriting to invalid kinds of subregister copies on some targets. I'm not sure if there is currently a generic way to easily check if a subregister index would be valid for the current use. The current set of TargetRegisterInfo::get*Class functions don't quite behave like I would expect (e.g. getSubClassWithSubReg returns the maximal register class rather than the minimal), so I'm not sure how to make the generic test keep searching if SrcRC:SrcSubReg is a valid replacement for DefRC:DefSubReg. Making the default implementation to check for simple copies breaks a variety of ARM and x86 tests by producing illegal subregister uses. The ARM tests are not actually changed since it should still be using the same sharesSameRegisterFile implementation, this just relaxes them to not check for specific registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
a5e772ea93
commit
b10121bd9d
@ -502,6 +502,15 @@ public:
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getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B, unsigned Idx) const;
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// For a copy-like instruction that defines a register of class DefRC with
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// subreg index DefSubReg, reading from another source with class SrcRC and
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// subregister SrcSubReg return true if this is a preferrable copy
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// instruction or an earlier use should be used.
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virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) const;
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/// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
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/// supports the sub-register index Idx.
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/// If no such sub-class exists, return NULL.
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@ -577,36 +577,6 @@ bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
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return TII->optimizeCondBranch(MI);
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}
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/// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
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/// share the same register file.
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static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
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const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) {
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// Same register class.
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if (DefRC == SrcRC)
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return true;
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// Both operands are sub registers. Check if they share a register class.
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unsigned SrcIdx, DefIdx;
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if (SrcSubReg && DefSubReg)
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return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
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SrcIdx, DefIdx) != nullptr;
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// At most one of the register is a sub register, make it Src to avoid
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// duplicating the test.
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if (!SrcSubReg) {
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std::swap(DefSubReg, SrcSubReg);
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std::swap(DefRC, SrcRC);
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}
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// One of the register is a sub register, check if we can get a superclass.
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if (SrcSubReg)
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return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
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// Plain copy.
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return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
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}
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/// \brief Try to find the next source that share the same register file
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/// for the value defined by \p Reg and \p SubReg.
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/// When true is returned, the \p RewriteMap can be used by the client to
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@ -687,10 +657,8 @@ bool PeepholeOptimizer::findNextSource(unsigned Reg, unsigned SubReg,
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return false;
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const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
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// If this source does not incur a cross register bank copy, use it.
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ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, SubReg, SrcRC,
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CurSrcPair.SubReg);
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ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC,
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CurSrcPair.SubReg);
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} while (!ShouldRewrite);
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// Continue looking for new sources...
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@ -265,6 +265,47 @@ getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
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return BestRC;
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}
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/// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
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/// share the same register file.
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static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
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const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) {
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// Same register class.
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if (DefRC == SrcRC)
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return true;
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// Both operands are sub registers. Check if they share a register class.
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unsigned SrcIdx, DefIdx;
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if (SrcSubReg && DefSubReg) {
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return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
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SrcIdx, DefIdx) != nullptr;
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}
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// At most one of the register is a sub register, make it Src to avoid
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// duplicating the test.
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if (!SrcSubReg) {
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std::swap(DefSubReg, SrcSubReg);
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std::swap(DefRC, SrcRC);
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}
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// One of the register is a sub register, check if we can get a superclass.
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if (SrcSubReg)
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return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
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// Plain copy.
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return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
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}
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bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) const {
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// If this source does not incur a cross register bank copy, use it.
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return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
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}
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// Compute target-independent register allocator hints to help eliminate copies.
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void
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TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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@ -392,6 +392,30 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
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}
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}
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bool SIRegisterInfo::shouldRewriteCopySrc(
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const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) const {
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// We want to prefer the smallest register class possible, so we don't want to
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// stop and rewrite on anything that looks like a subregister
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// extract. Operations mostly don't care about the super register class, so we
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// only want to stop on the most basic of copies between the smae register
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// class.
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//
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// e.g. if we have something like
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// vreg0 = ...
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// vreg1 = ...
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// vreg2 = REG_SEQUENCE vreg0, sub0, vreg1, sub1, vreg2, sub2
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// vreg3 = COPY vreg2, sub0
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//
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// We want to look through the COPY to find:
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// => vreg3 = COPY vreg0
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// Plain copy.
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return getCommonSubClass(DefRC, SrcRC) != nullptr;
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}
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unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
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const TargetRegisterClass *SubRC,
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unsigned Channel) const {
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@ -75,6 +75,11 @@ public:
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const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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unsigned SubIdx) const;
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bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) const override;
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/// \p Channel This is the register channel (e.g. a value from 0-16), not the
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/// SubReg index.
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/// \returns The sub-register of Reg that is in Channel.
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@ -147,11 +147,24 @@ endif:
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ret void
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}
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; FIXME: and 0 should be replaced witht copy
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; FUNC-LABEL: {{^}}v_and_constant_i64:
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; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207
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; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], {{v[0-9]+}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], {{v[0-9]+}}
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; SI: buffer_store_dwordx2
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define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 1231231234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Should replace and 0
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; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant:
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; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}}
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define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load i64, i64 addrspace(1)* %aptr, align 8
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%and = and i64 %a, 1234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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@ -35,14 +35,11 @@ define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 {
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ret void
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}
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; FIXME: Shuffling to new superregister
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; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Y:[0-9]+]]:[[REG_X:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI-DAG: v_mov_b32_e32 v[[COPY_REG_Y:[0-9]+]], v[[REG_Y]]
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; CI-DAG: v_mov_b32_e32 v[[COPY_REG_Z:[0-9]+]], v[[REG_Z]]
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[COPY_REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[COPY_REG_Y]]
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Z:[0-9]+]]:[[REG_W:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[REG_Y]]
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; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD1]], v[[ADD0]]
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; CI: buffer_store_dword v[[ADD2]]
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; CI: s_endpgm
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@ -64,11 +61,15 @@ define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 {
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ret void
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}
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; FIXME: the v_lshl_b64 x, x, 32 is a bad way of doing a copy
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; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
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; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
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; CI: v_lshr_b64 v{{\[}}[[Y_COPY:[0-9]+]]:{{[0-9]+\]}}, v{{\[}}[[REG_X]]:[[REG_Y]]{{\]}}, 32
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; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[ADD0]]
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; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[Y_COPY]], v[[ADD0]]
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; CI: buffer_store_dword v[[ADD1]]
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; CI: s_endpgm
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define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
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@ -140,13 +141,21 @@ define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 {
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; CI-LABEL: {{^}}simple_read2_v16f32_superreg:
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:15 offset1:14{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:13 offset1:12{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:11 offset1:10{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:9 offset1:8{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
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; CI-NOT: v_mov_b32
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; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
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; CI-NOT: v_mov_b32
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; CI: s_waitcnt lgkmcnt(0)
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; CI: buffer_store_dword
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@ -391,13 +391,12 @@ define void @global_truncstore_v2f32_to_v2f16(<2 x half> addrspace(1)* %out, <2
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ret void
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}
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; FIXME: Shouldn't do 4th conversion
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; GCN-LABEL: {{^}}global_truncstore_v3f32_to_v3f16:
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; GCN: buffer_load_dwordx4
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN-NOT: v_cvt_f16_f32_e32
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; GCN: buffer_store_short
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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@ -476,38 +475,38 @@ define void @global_truncstore_v8f32_to_v8f16(<8 x half> addrspace(1)* %out, <8
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: v_cvt_f16_f32_e32
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN: buffer_store_short
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: v_cvt_f16_f32_e32
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
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; GCN-DAG: buffer_store_short
|
||||
; GCN: s_endpgm
|
||||
define void @global_truncstore_v16f32_to_v16f16(<16 x half> addrspace(1)* %out, <16 x float> addrspace(1)* %in) #0 {
|
||||
%val = load <16 x float>, <16 x float> addrspace(1)* %in
|
||||
|
||||
@ -21,12 +21,9 @@ define void @round_f64(double addrspace(1)* %out, double %x) #0 {
|
||||
; SI-DAG: v_cmp_eq_i32
|
||||
|
||||
; SI-DAG: s_mov_b32 [[BFIMASK:s[0-9]+]], 0x7fffffff
|
||||
; SI-DAG: v_cmp_gt_i32_e64
|
||||
; SI-DAG: v_cmp_gt_i32_e32
|
||||
; SI-DAG: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[BFIMASK]]
|
||||
|
||||
; SI-DAG: v_cmp_gt_i32_e64
|
||||
|
||||
|
||||
; SI: buffer_store_dwordx2
|
||||
; SI: s_endpgm
|
||||
define void @v_round_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 {
|
||||
|
||||
36
test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
Normal file
36
test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
Normal file
@ -0,0 +1,36 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
; Check that when mubuf addr64 instruction is handled in moveToVALU
|
||||
; from the pointer, dead register writes are not emitted.
|
||||
|
||||
; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
|
||||
|
||||
; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add:
|
||||
; GCN: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
|
||||
; GCN: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}}
|
||||
|
||||
; GCN-NOT: v_mov_b32
|
||||
; GCN: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]]
|
||||
; GCN-NEXT: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]]
|
||||
; GCN-NOT: v_mov_b32
|
||||
|
||||
; GCN: v_add_i32_e32 v[[PTRLO:[0-9]+]], vcc, v[[LDPTRLO]], v[[VARG1LO]]
|
||||
; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]]
|
||||
; GCN: buffer_load_ubyte v{{[0-9]+}}, v{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}},
|
||||
|
||||
define void @clobber_vgpr_pair_pointer_add(i64 %arg1, i8 addrspace(1)* addrspace(1)* %ptrarg, i32 %arg3) #0 {
|
||||
bb:
|
||||
%tmp = icmp sgt i32 %arg3, 0
|
||||
br i1 %tmp, label %bb4, label %bb17
|
||||
|
||||
bb4:
|
||||
%tmp14 = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %ptrarg
|
||||
%tmp15 = getelementptr inbounds i8, i8 addrspace(1)* %tmp14, i64 %arg1
|
||||
%tmp16 = load volatile i8, i8 addrspace(1)* %tmp15
|
||||
br label %bb17
|
||||
|
||||
bb17:
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
@ -2,11 +2,15 @@
|
||||
; RUN: llc -mtriple=armeb-eabi -float-abi=soft -mattr=+neon %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
|
||||
|
||||
define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK: vcombine8
|
||||
; CHECK-LE: vmov r0, r1, d16
|
||||
; CHECK-LE: vmov r2, r3, d17
|
||||
; CHECK-BE: vmov r1, r0, d16
|
||||
; CHECK-BE: vmov r3, r2, d17
|
||||
; CHECK-LABEL: vcombine8
|
||||
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
|
||||
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
|
||||
|
||||
; CHECK-LE-DAG: vmov r0, r1, [[LD0]]
|
||||
; CHECK-LE-DAG: vmov r2, r3, [[LD1]]
|
||||
|
||||
; CHECK-BE-DAG: vmov r1, r0, d16
|
||||
; CHECK-BE-DAG: vmov r3, r2, d17
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
||||
@ -14,11 +18,15 @@ define <16 x i8> @vcombine8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
}
|
||||
|
||||
define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
; CHECK: vcombine16
|
||||
; CHECK-LE: vmov r0, r1, d16
|
||||
; CHECK-LE: vmov r2, r3, d17
|
||||
; CHECK-BE: vmov r1, r0, d16
|
||||
; CHECK-BE: vmov r3, r2, d17
|
||||
; CHECK-LABEL: vcombine16
|
||||
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
|
||||
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
|
||||
|
||||
; CHECK-LE-DAG: vmov r0, r1, [[LD0]]
|
||||
; CHECK-LE-DAG: vmov r2, r3, [[LD1]]
|
||||
|
||||
; CHECK-BE-DAG: vmov r1, r0, d16
|
||||
; CHECK-BE-DAG: vmov r3, r2, d17
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>, <4 x i16>* %B
|
||||
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
@ -26,9 +34,14 @@ define <8 x i16> @vcombine16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
}
|
||||
|
||||
define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
; CHECK: vcombine32
|
||||
; CHECK-LE: vmov r0, r1, d16
|
||||
; CHECK-LE: vmov r2, r3, d17
|
||||
; CHECK-LABEL: vcombine32
|
||||
|
||||
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
|
||||
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
|
||||
|
||||
; CHECK-LE: vmov r0, r1, [[LD0]]
|
||||
; CHECK-LE: vmov r2, r3, [[LD1]]
|
||||
|
||||
; CHECK-BE: vmov r1, r0, d16
|
||||
; CHECK-BE: vmov r3, r2, d17
|
||||
%tmp1 = load <2 x i32>, <2 x i32>* %A
|
||||
@ -38,9 +51,14 @@ define <4 x i32> @vcombine32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
}
|
||||
|
||||
define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
; CHECK: vcombinefloat
|
||||
; CHECK-LE: vmov r0, r1, d16
|
||||
; CHECK-LE: vmov r2, r3, d17
|
||||
; CHECK-LABEL: vcombinefloat
|
||||
|
||||
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
|
||||
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
|
||||
|
||||
; CHECK-LE: vmov r0, r1, [[LD0]]
|
||||
; CHECK-LE: vmov r2, r3, [[LD1]]
|
||||
|
||||
; CHECK-BE: vmov r1, r0, d16
|
||||
; CHECK-BE: vmov r3, r2, d17
|
||||
%tmp1 = load <2 x float>, <2 x float>* %A
|
||||
@ -50,11 +68,15 @@ define <4 x float> @vcombinefloat(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
}
|
||||
|
||||
define <2 x i64> @vcombine64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
|
||||
; CHECK: vcombine64
|
||||
; CHECK-LE: vmov r0, r1, d16
|
||||
; CHECK-LE: vmov r2, r3, d17
|
||||
; CHECK-BE: vmov r1, r0, d16
|
||||
; CHECK-BE: vmov r3, r2, d17
|
||||
; CHECK-LABEL: vcombine64
|
||||
; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
|
||||
; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
|
||||
|
||||
; CHECK-LE: vmov r0, r1, [[LD0]]
|
||||
; CHECK-LE: vmov r2, r3, [[LD1]]
|
||||
|
||||
; CHECK-BE: vmov r1, r0, [[LD0]]
|
||||
; CHECK-BE: vmov r3, r2, [[LD1]]
|
||||
%tmp1 = load <1 x i64>, <1 x i64>* %A
|
||||
%tmp2 = load <1 x i64>, <1 x i64>* %B
|
||||
%tmp3 = shufflevector <1 x i64> %tmp1, <1 x i64> %tmp2, <2 x i32> <i32 0, i32 1>
|
||||
|
||||
@ -20,11 +20,11 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vtrni8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vtrni8_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vtrn.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
@ -52,11 +52,11 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
define <8 x i16> @vtrni16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
; CHECK-LABEL: vtrni16_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vtrn.16 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vtrn.16 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>, <4 x i16>* %B
|
||||
@ -84,11 +84,11 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
define <4 x i32> @vtrni32_Qres(<2 x i32>* %A, <2 x i32>* %B) nounwind {
|
||||
; CHECK-LABEL: vtrni32_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vtrn.32 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <2 x i32>, <2 x i32>* %A
|
||||
%tmp2 = load <2 x i32>, <2 x i32>* %B
|
||||
@ -116,11 +116,11 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
define <4 x float> @vtrnf_Qres(<2 x float>* %A, <2 x float>* %B) nounwind {
|
||||
; CHECK-LABEL: vtrnf_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vtrn.32 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vtrn.32 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <2 x float>, <2 x float>* %A
|
||||
%tmp2 = load <2 x float>, <2 x float>* %B
|
||||
@ -281,11 +281,11 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vtrni8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vtrni8_undef_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vtrn.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vtrn.8 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
|
||||
@ -20,11 +20,11 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vuzpi8_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vuzp.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
@ -52,11 +52,11 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
; CHECK-LABEL: vuzpi16_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vuzp.16 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vuzp.16 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>, <4 x i16>* %B
|
||||
@ -220,11 +220,11 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vuzpi8_undef_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vuzp.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
|
||||
@ -20,11 +20,11 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vzipi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vzipi8_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vzip.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vzip.8 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
@ -52,11 +52,11 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
define <8 x i16> @vzipi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
|
||||
; CHECK-LABEL: vzipi16_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vzip.16 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vzip.16 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <4 x i16>, <4 x i16>* %A
|
||||
%tmp2 = load <4 x i16>, <4 x i16>* %B
|
||||
@ -220,11 +220,11 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
define <16 x i8> @vzipi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
; CHECK-LABEL: vzipi8_undef_Qres:
|
||||
; CHECK: @ BB#0:
|
||||
; CHECK-NEXT: vldr d17, [r1]
|
||||
; CHECK-NEXT: vldr d16, [r0]
|
||||
; CHECK-NEXT: vzip.8 d16, d17
|
||||
; CHECK-NEXT: vmov r0, r1, d16
|
||||
; CHECK-NEXT: vmov r2, r3, d17
|
||||
; CHECK-NEXT: vldr [[LDR1:d[0-9]+]], [r1]
|
||||
; CHECK-NEXT: vldr [[LDR0:d[0-9]+]], [r0]
|
||||
; CHECK-NEXT: vzip.8 [[LDR0]], [[LDR1]]
|
||||
; CHECK-NEXT: vmov r0, r1, [[LDR0]]
|
||||
; CHECK-NEXT: vmov r2, r3, [[LDR1]]
|
||||
; CHECK-NEXT: mov pc, lr
|
||||
%tmp1 = load <8 x i8>, <8 x i8>* %A
|
||||
%tmp2 = load <8 x i8>, <8 x i8>* %B
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user