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[ARM64] Port over missing subtarget features, and CPU definitions from AArch64.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
James Molloy 2014-04-14 17:38:00 +00:00
parent 1f1bced6e7
commit b1138a1313
3 changed files with 52 additions and 5 deletions
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35
lib/Target/ARM64/ARM64.td
View File

@ -20,6 +20,15 @@ include "llvm/Target/Target.td"
// ARM64 Subtarget features.
//
def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
"Enable ARMv8 FP">;
def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
"Enable cryptographic instructions">;
/// Cyclone has register move instructions which are "free".
def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
"Has zereo-cycle register moves">;
@ -49,9 +58,31 @@ def ARM64InstrInfo : InstrInfo;
//
include "ARM64SchedCyclone.td"
def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
"Cortex-A53 ARM processors",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto]>;
def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto]>;
def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
"Cyclone",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto,
FeatureZCRegMove, FeatureZCZeroing]>;
def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, FeatureNEON]>;
def : ProcessorModel<"cortex-a53", NoSchedModel, [ProcA53]>;
def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
//===----------------------------------------------------------------------===//
// Assembly parser

9
lib/Target/ARM64/ARM64Subtarget.cpp
View File

@ -26,12 +26,15 @@ using namespace llvm;
ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
const std::string &FS)
: ARM64GenSubtargetInfo(TT, CPU, FS), HasZeroCycleRegMove(false),
HasZeroCycleZeroing(false), CPUString(CPU), TargetTriple(TT) {
: ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
HasFPARMv8(false), HasNEON(false), HasCrypto(false),
HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
CPUString(CPU), TargetTriple(TT) {
// Determine default and user-specified characteristics
// FIXME: Make this darwin-only.
if (CPUString.empty())
// We default to Cyclone for now.
// We default to Cyclone for now, on Darwin.
CPUString = "cyclone";
ParseSubtargetFeatures(CPUString, FS);

13
lib/Target/ARM64/ARM64Subtarget.h
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@ -27,6 +27,15 @@ class StringRef;
class ARM64Subtarget : public ARM64GenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
ARMProcFamilyEnum ARMProcFamily;
bool HasFPARMv8;
bool HasNEON;
bool HasCrypto;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove;
@ -51,6 +60,10 @@ public:
bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }