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ARM64: print fp immediates without using scientific notation.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-30 16:13:34 +00:00
parent 83286f081d
commit b1c1b8a78d
9 changed files with 28 additions and 30 deletions
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10
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
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@ -1221,12 +1221,10 @@ void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
const MCOperand &MO = MI->getOperand(OpNum);
O << '#';
if (MO.isFPImm())
// FIXME: Should this ever happen?
O << MO.getFPImm();
else
O << ARM64_AM::getFPImmFloat(MO.getImm());
float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm());
// 8 decimal places are enough to perfectly represent permitted floats.
O << format("#%.8f", FPImm);
}
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {

4
test/CodeGen/ARM64/fast-isel-materialize.ll
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@ -3,14 +3,14 @@
; Materialize using fmov
define void @float_(float* %value) {
; CHECK: @float_
; CHECK: fmov s0, #1.250000e+00
; CHECK: fmov s0, #1.25000000
store float 1.250000e+00, float* %value, align 4
ret void
}
define void @double_(double* %value) {
; CHECK: @double_
; CHECK: fmov d0, #1.250000e+00
; CHECK: fmov d0, #1.25000000
store double 1.250000e+00, double* %value, align 8
ret void
}

6
test/CodeGen/ARM64/vector-imm.ll
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@ -42,7 +42,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
define <2 x double> @foo(<2 x double> %bar) nounwind {
; CHECK: foo
; CHECK: fmov.2d v1, #1.000000e+00
; CHECK: fmov.2d v1, #1.0000000
%add = fadd <2 x double> %bar, <double 1.0, double 1.0>
ret <2 x double> %add
}
@ -122,13 +122,13 @@ ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_4s_imm_t11:
; CHECK: fmov.4s v0, #-3.281250e-01
; CHECK: fmov.4s v0, #-0.32812500
ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
}
define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {
entry:
; CHECK-LABEL: movi_2d_imm_t12:
; CHECK: fmov.2d v0, #-1.718750e-01
; CHECK: fmov.2d v0, #-0.17187500
ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
}

2
test/CodeGen/ARM64/vector-insertion.ll
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@ -25,7 +25,7 @@ entry:
ret void
; CHECK-LABEL: test1f
; CHECK: fmov s[[TEMP:[0-9]+]], #1.000000e+00
; CHECK: fmov s[[TEMP:[0-9]+]], #1.0000000
; CHECK: dup.4s v[[TEMP2:[0-9]+]], v[[TEMP]][0]
; CHECK: ins.s v[[TEMP2]][0], v0[0]
; CHECK: str q[[TEMP2]], [x0]

6
test/MC/ARM64/advsimd.s
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@ -816,13 +816,13 @@ foo:
fmov.2d v0, #1.250000e-01
; CHECK: fmov.2d v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x6f]
; CHECK: fmov.2d v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x6f]
fmov.2s v0, #1.250000e-01
fmov.4s v0, #1.250000e-01
; CHECK: fmov.2s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x0f]
; CHECK: fmov.4s v0, #1.250000e-01 ; encoding: [0x00,0xf4,0x02,0x4f]
; CHECK: fmov.2s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x0f]
; CHECK: fmov.4s v0, #0.12500000 ; encoding: [0x00,0xf4,0x02,0x4f]
orr.2s v0, #1
orr.2s v0, #1, lsl #0

14
test/MC/ARM64/fp-encoding.s
View File

@ -333,13 +333,13 @@ foo:
fmov s2, #0.0
fmov d2, #0.0
; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e]
; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e]
; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e]
; CHECK: fmov d1, #1.250000e-01 ; encoding: [0x01,0x10,0x68,0x1e]
; CHECK: fmov d1, #-4.843750e-01 ; encoding: [0x01,0xf0,0x7b,0x1e]
; CHECK: fmov d1, #4.843750e-01 ; encoding: [0x01,0xf0,0x6b,0x1e]
; CHECK: fmov d3, #3.000000e+00 ; encoding: [0x03,0x10,0x61,0x1e]
; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e]
; CHECK: fmov d1, #0.12500000 ; encoding: [0x01,0x10,0x68,0x1e]
; CHECK: fmov d1, #-0.48437500 ; encoding: [0x01,0xf0,0x7b,0x1e]
; CHECK: fmov d1, #0.48437500 ; encoding: [0x01,0xf0,0x6b,0x1e]
; CHECK: fmov d3, #3.00000000 ; encoding: [0x03,0x10,0x61,0x1e]
; CHECK: fmov s2, wzr ; encoding: [0xe2,0x03,0x27,0x1e]
; CHECK: fmov d2, xzr ; encoding: [0xe2,0x03,0x67,0x9e]

2
test/MC/ARM64/optional-hash.s
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@ -13,7 +13,7 @@ adds x3, x4, 1024, lsl 12
add sp, x2, x3, uxtx 0
; FP immediates
; CHECK: fmov s1, #1.250000e-01 ; encoding: [0x01,0x10,0x28,0x1e]
; CHECK: fmov s1, #0.12500000 ; encoding: [0x01,0x10,0x28,0x1e]
fmov s1, 0.125
; Barrier operand

6
test/MC/Disassembler/ARM64/advsimd.txt
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@ -568,13 +568,13 @@
0x00 0xf4 0x02 0x6f
# CHECK: fmov.2d v0, #1.250000e-01
# CHECK: fmov.2d v0, #0.12500000
0x00 0xf4 0x02 0x0f
0x00 0xf4 0x02 0x4f
# CHECK: fmov.2s v0, #1.250000e-01
# CHECK: fmov.4s v0, #1.250000e-01
# CHECK: fmov.2s v0, #0.12500000
# CHECK: fmov.4s v0, #0.12500000
0x20 0x14 0x00 0x0f
0x20 0x34 0x00 0x0f

8
test/MC/Disassembler/ARM64/scalar-fp.txt
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@ -184,10 +184,10 @@
0x01 0xf0 0x7b 0x1e
0x01 0xf0 0x6b 0x1e
# CHECK: fmov s1, #1.250000e-01
# CHECK: fmov d1, #1.250000e-01
# CHECK: fmov d1, #-4.843750e-01
# CHECK: fmov d1, #4.843750e-01
# CHECK: fmov s1, #0.12500000
# CHECK: fmov d1, #0.12500000
# CHECK: fmov d1, #-0.48437500
# CHECK: fmov d1, #0.48437500
0x41 0x40 0x20 0x1e
0x41 0x40 0x60 0x1e