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Custom lower SCALAR_TO_VECTOR into lve*x.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26868 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-03-19 06:55:52 +00:00
parent 4d3abee618
commit b2177b9405
3 changed files with 37 additions and 9 deletions
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20
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -184,8 +184,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
}
setSetCCResultContents(ZeroOrOneSetCCResult);
@ -208,6 +208,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
case PPCISD::STFIWX: return "PPCISD::STFIWX";
case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
case PPCISD::LVE_X: return "PPCISD::LVE_X";
case PPCISD::Hi: return "PPCISD::Hi";
case PPCISD::Lo: return "PPCISD::Lo";
case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
@ -550,6 +551,21 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
}
return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
case ISD::SCALAR_TO_VECTOR: {
// Create a stack slot that is 16-byte aligned.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
int FrameIdx = FrameInfo->CreateStackObject(16, 16);
SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
// Store the input value into Value#0 of the stack slot.
unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8;
FIdx = DAG.getNode(ISD::ADD, MVT::i32, FIdx,
DAG.getConstant(16-InSize, MVT::i32));
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx,
DAG.getSrcValue(NULL));
}
}
return SDOperand();
}

8
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -48,6 +48,14 @@ namespace llvm {
// three v4f32 operands and producing a v4f32 result.
VMADDFP, VNMSUBFP,
/// LVE_X - The PPC LVE*X instructions. The size of the element loaded is
/// the size of the element type of the vector result. The element loaded
/// depends on the alignment of the input pointer.
///
/// The first operand is a token chain, the second is the address to load
/// the third is the SRCVALUE node.
LVE_X,
/// Hi/Lo - These represent the high and low 16-bit parts of a global
/// address respectively. These nodes have two operands, the first of
/// which must be a TargetGlobalAddress, and the second of which must be a

18
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -45,6 +45,8 @@ def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
def PPClve_x : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
// amounts. These nodes are generated by the multi-precision shift code.
def PPCsrl : SDNode<"PPCISD::SRL" , SDT_PPCShiftOp>;
@ -451,15 +453,15 @@ def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
"lvebx $vD, $base, $rA", LdStGeneral,
def LVEBX: XForm_1<31, 7, (ops VRRC:$vD, memrr:$src),
"lvebx $vD, $src", LdStGeneral,
[]>;
def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
"lvehx $vD, $base, $rA", LdStGeneral,
[]>;
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, GPRC:$base, GPRC:$rA),
"lvewx $vD, $base, $rA", LdStGeneral,
def LVEHX: XForm_1<31, 39, (ops VRRC:$vD, memrr:$src),
"lvehx $vD, $src", LdStGeneral,
[]>;
def LVEWX: XForm_1<31, 71, (ops VRRC:$vD, memrr:$src),
"lvewx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
def LVX : XForm_1<31, 103, (ops VRRC:$vD, memrr:$src),
"lvx $vD, $src", LdStGeneral,
[(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
@ -1149,6 +1151,8 @@ def : Pat<(v4i32 (load xoaddr:$src)),
(v4i32 (LVX xoaddr:$src))>;
def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
(STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
(v4i32 (LVEWX xoaddr:$src))>;
def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;