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Minor tweak. Instead of generating:

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movl 32(%esp), %eax
        cmpl $1, %eax
        je LBB1_1       #bb
LBB1_4: #entry
        cmpl $2, %eax
        je LBB1_2       #bb2
        jmp LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb

notice that we would miss the fall through and emit this instead:

        movl 32(%esp), %eax
        cmpl $2, %eax
        je LBB1_2       #bb2
LBB1_4: #entry
        cmpl $1, %eax
        jne LBB1_3      #UnifiedReturnBlock
LBB1_1: #bb


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31130 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-10-23 18:38:22 +00:00
parent 66ebf0973d
commit b354343af7
1 changed files with 13 additions and 0 deletions
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13
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -936,6 +936,19 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
// use bit manipulation to do two compares at once. For example:
// "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
// Rearrange the case blocks so that the last one falls through if possible.
if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
// The last case block won't fall through into 'NextBlock' if we emit the
// branches in this order. See if rearranging a case value would help.
for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
if (Cases[i].second == NextBlock) {
std::swap(Cases[i], Cases.back());
break;
}
}
}
// Create a CaseBlock record representing a conditional branch to
// the Case's target mbb if the value being switched on SV is equal
// to C.