RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-04 01:43:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Convert the last remaining users of the non-APInt form of

Browse Source 
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-02-27 01:23:58 +00:00
parent e6be34a53e
commit b3564aa836
4 changed files with 39 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/llvm/CodeGen/SelectionDAG.h
View File

@ -573,12 +573,6 @@ public:
void ComputeMaskedBits(SDOperand Op, const APInt &Mask, APInt &KnownZero,
APInt &KnownOne, unsigned Depth = 0) const;
/// ComputeMaskedBits - This is a wrapper around the APInt-using
/// form of ComputeMaskedBits for use by clients that haven't been converted
/// to APInt yet.
void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
uint64_t &KnownOne, unsigned Depth = 0) const;
/// ComputeNumSignBits - Return the number of times the sign bit of the
/// register is replicated into the other bits. We know that at least 1 bit
/// is always equal to the sign bit (itself), but other cases can give us

50
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1507,25 +1507,6 @@ void SelectionDAG::ComputeMaskedBits(SDOperand Op, const APInt &Mask,
}
}
/// ComputeMaskedBits - This is a wrapper around the APInt-using
/// form of ComputeMaskedBits for use by clients that haven't been converted
/// to APInt yet.
void SelectionDAG::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
uint64_t &KnownZero, uint64_t &KnownOne,
unsigned Depth) const {
// The masks are not wide enough to represent this type! Should use APInt.
if (Op.getValueType() == MVT::i128)
return;
unsigned NumBits = MVT::getSizeInBits(Op.getValueType());
APInt APIntMask(NumBits, Mask);
APInt APIntKnownZero(NumBits, 0);
APInt APIntKnownOne(NumBits, 0);
ComputeMaskedBits(Op, APIntMask, APIntKnownZero, APIntKnownOne, Depth);
KnownZero = APIntKnownZero.getZExtValue();
KnownOne = APIntKnownOne.getZExtValue();
}
/// ComputeNumSignBits - Return the number of times the sign bit of the
/// register is replicated into the other bits. We know that at least 1 bit
/// is always equal to the sign bit (itself), but other cases can give us
@ -1637,18 +1618,18 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
// Special case decrementing a value (ADD X, -1):
if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
if (CRHS->isAllOnesValue()) {
uint64_t KnownZero, KnownOne;
uint64_t Mask = MVT::getIntVTBitMask(VT);
APInt KnownZero, KnownOne;
APInt Mask = APInt::getAllOnesValue(VTBits);
ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set.
if ((KnownZero|1) == Mask)
if ((KnownZero | APInt(VTBits, 1)) == Mask)
return VTBits;
// If we are subtracting one from a positive number, there is no carry
// out of the result.
if (KnownZero & MVT::getIntVTSignBit(VT))
if (KnownZero.isNegative())
return Tmp;
}
@ -1664,17 +1645,17 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
// Handle NEG.
if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
if (CLHS->getValue() == 0) {
uint64_t KnownZero, KnownOne;
uint64_t Mask = MVT::getIntVTBitMask(VT);
APInt KnownZero, KnownOne;
APInt Mask = APInt::getAllOnesValue(VTBits);
ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set.
if ((KnownZero|1) == Mask)
if ((KnownZero | APInt(VTBits, 1)) == Mask)
return VTBits;
// If the input is known to be positive (the sign bit is known clear),
// the output of the NEG has the same number of sign bits as the input.
if (KnownZero & MVT::getIntVTSignBit(VT))
if (KnownZero.isNegative())
return Tmp2;
// Otherwise, we treat this like a SUB.
@ -1718,14 +1699,13 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
// Finally, if we can prove that the top bits of the result are 0's or 1's,
// use this information.
uint64_t KnownZero, KnownOne;
uint64_t Mask = MVT::getIntVTBitMask(VT);
APInt KnownZero, KnownOne;
APInt Mask = APInt::getAllOnesValue(VTBits);
ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
uint64_t SignBit = MVT::getIntVTSignBit(VT);
if (KnownZero & SignBit) { // SignBit is 0
if (KnownZero.isNegative()) { // sign bit is 0
Mask = KnownZero;
} else if (KnownOne & SignBit) { // SignBit is 1;
} else if (KnownOne.isNegative()) { // sign bit is 1;
Mask = KnownOne;
} else {
// Nothing known.
@ -1734,11 +1714,11 @@ unsigned SelectionDAG::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
// Okay, we know that the sign bit in Mask is set. Use CLZ to determine
// the number of identical bits in the top of the input value.
Mask ^= ~0ULL;
Mask <<= 64-VTBits;
Mask = ~Mask;
Mask <<= Mask.getBitWidth()-VTBits;
// Return # leading zeros. We use 'min' here in case Val was zero before
// shifting. We don't want to return '64' as for an i32 "0".
return std::min(VTBits, CountLeadingZeros_64(Mask));
return std::min(VTBits, Mask.countLeadingZeros());
}

10
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -424,12 +424,12 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
SDOperand Op0 = N->getOperand(0);
SDOperand Op1 = N->getOperand(1);
uint64_t LKZ, LKO, RKZ, RKO;
CurDAG->ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
CurDAG->ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
APInt LKZ, LKO, RKZ, RKO;
CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
unsigned TargetMask = LKZ;
unsigned InsertMask = RKZ;
unsigned TargetMask = LKZ.getZExtValue();
unsigned InsertMask = RKZ.getZExtValue();
if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
unsigned Op0Opc = Op0.getOpcode();

30
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -738,12 +738,16 @@ bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
// If this is an or of disjoint bitfields, we can codegen this as an add
// (for better address arithmetic) if the LHS and RHS of the OR are provably
// disjoint.
uint64_t LHSKnownZero, LHSKnownOne;
uint64_t RHSKnownZero, RHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
APInt LHSKnownZero, LHSKnownOne;
APInt RHSKnownZero, RHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0),
APInt::getAllOnesValue(32),
LHSKnownZero, LHSKnownOne);
if (LHSKnownZero) {
DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
if (LHSKnownZero.getBoolValue()) {
DAG.ComputeMaskedBits(N.getOperand(1),
APInt::getAllOnesValue(32),
RHSKnownZero, RHSKnownOne);
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
if ((LHSKnownZero | RHSKnownZero) == ~0U) {
@ -793,9 +797,11 @@ bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
// If this is an or of disjoint bitfields, we can codegen this as an add
// (for better address arithmetic) if the LHS and RHS of the OR are
// provably disjoint.
uint64_t LHSKnownZero, LHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
APInt LHSKnownZero, LHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0),
APInt::getAllOnesValue(32),
LHSKnownZero, LHSKnownOne);
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
Base = N.getOperand(0);
@ -901,9 +907,11 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
// If this is an or of disjoint bitfields, we can codegen this as an add
// (for better address arithmetic) if the LHS and RHS of the OR are
// provably disjoint.
uint64_t LHSKnownZero, LHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
APInt LHSKnownZero, LHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0),
APInt::getAllOnesValue(32),
LHSKnownZero, LHSKnownOne);
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
// If all of the bits are known zero on the LHS or RHS, the add won't
// carry.
Base = N.getOperand(0);