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[InstCombine] Add support for vector srem->urem.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2017-04-17 01:51:24 +00:00
parent 2b555ede15
commit b39b99c0aa
2 changed files with 6 additions and 8 deletions
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12
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
View File

@ -1544,13 +1544,11 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
// If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a urem.
if (I.getType()->isIntegerTy()) {
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask, 0, &I) &&
MaskedValueIsZero(Op0, Mask, 0, &I)) {
// X srem Y -> X urem Y, iff X and Y don't have sign bit set
return BinaryOperator::CreateURem(Op0, Op1, I.getName());
}
APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits()));
if (MaskedValueIsZero(Op1, Mask, 0, &I) &&
MaskedValueIsZero(Op0, Mask, 0, &I)) {
// X srem Y -> X urem Y, iff X and Y don't have sign bit set
return BinaryOperator::CreateURem(Op0, Op1, I.getName());
}
// If it's a constant vector, flip any negative values positive.

2
test/Transforms/InstCombine/rem.ll
View File

@ -586,7 +586,7 @@ define i32 @test22(i32 %A) {
define <2 x i32> @test23(<2 x i32> %A) {
; CHECK-LABEL: @test23(
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: [[MUL:%.*]] = srem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: [[MUL:%.*]] = urem <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
; CHECK-NEXT: ret <2 x i32> [[MUL]]
;
%and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>