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Try operation promotion only if regular dag combine and target-specific ones failed to do anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102492 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1011,7 +1011,7 @@ void DAGCombiner::Run(CombineLevel AtLevel) {
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}
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SDValue DAGCombiner::visit(SDNode *N) {
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switch(N->getOpcode()) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::TokenFactor: return visitTokenFactor(N);
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case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
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@ -1096,6 +1096,35 @@ SDValue DAGCombiner::combine(SDNode *N) {
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}
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}
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// If nothing happened still, try promoting the operation.
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if (RV.getNode() == 0) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::ADD:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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RV = PromoteIntBinOp(SDValue(N, 0));
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break;
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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RV = PromoteIntShiftOp(SDValue(N, 0));
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break;
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case ISD::SIGN_EXTEND:
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case ISD::ZERO_EXTEND:
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case ISD::ANY_EXTEND:
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RV = PromoteExtend(SDValue(N, 0));
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break;
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case ISD::LOAD:
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if (PromoteLoad(SDValue(N, 0)))
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RV = SDValue(N, 0);
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break;
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}
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}
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// If N is a commutative binary node, try commuting it to enable more
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// sdisel CSE.
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if (RV.getNode() == 0 &&
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@ -1387,7 +1416,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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N0.getOperand(0).getOperand(1),
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N0.getOperand(1)));
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return PromoteIntBinOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitADDC(SDNode *N) {
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@ -1525,7 +1554,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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VT);
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}
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return PromoteIntBinOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitMUL(SDNode *N) {
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@ -1618,7 +1647,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
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if (RMUL.getNode() != 0)
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return RMUL;
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return PromoteIntBinOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitSDIV(SDNode *N) {
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@ -2264,7 +2293,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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}
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}
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return PromoteIntBinOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitOR(SDNode *N) {
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@ -2390,7 +2419,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
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if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
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return SDValue(Rot, 0);
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return PromoteIntBinOp(SDValue(N, 0));
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return SDValue();
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}
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/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
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@ -2699,7 +2728,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
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SimplifyDemandedBits(SDValue(N, 0)))
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return SDValue(N, 0);
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return PromoteIntBinOp(SDValue(N, 0));
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return SDValue();
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}
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/// visitShiftByConstant - Handle transforms common to the three shifts, when
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@ -2866,7 +2895,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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return NewSHL;
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}
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return PromoteIntShiftOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitSRA(SDNode *N) {
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@ -2986,7 +3015,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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return NewSRA;
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}
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return PromoteIntShiftOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitSRL(SDNode *N) {
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@ -3152,7 +3181,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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}
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}
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return PromoteIntShiftOp(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitCTLZ(SDNode *N) {
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@ -3550,7 +3579,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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DAG.SignBitIsZero(N0))
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return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
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return PromoteExtend(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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@ -3713,7 +3742,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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N0.getOperand(1)));
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}
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return PromoteExtend(SDValue(N, 0));
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return SDValue();
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}
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SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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@ -3849,7 +3878,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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return SCC;
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}
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return PromoteExtend(SDValue(N, 0));
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return SDValue();
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}
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/// GetDemandedBits - See if the specified operand can be simplified with the
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@ -5451,8 +5480,6 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) {
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if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
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return SDValue(N, 0);
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if (PromoteLoad(SDValue(N, 0)))
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return SDValue(N, 0);
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return SDValue();
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}
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