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Fix 80 column violations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58371 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-10-29 06:33:00 +00:00
parent 86813ce5fa
commit b3bc6352de
1 changed files with 2 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -1708,7 +1708,7 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
// The low part is sign extension of the input (which degenerates to a copy).
// The low part is sign extension of the input (degenerates to a copy).
Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
// The high part is obtained by SRA'ing all but one of the bits of low part.
unsigned LoSize = NVT.getSizeInBits();
@ -1822,7 +1822,7 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
// The low part is zero extension of the input (which degenerates to a copy).
// The low part is zero extension of the input (degenerates to a copy).
Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
} else {