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Fix a regression from 76124. Thumb1 instructions default to S bit being true.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76374 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-07-19 19:16:46 +00:00
parent 45d34fe358
commit b46aaa3874
2 changed files with 19 additions and 13 deletions
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5
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -198,6 +198,11 @@ const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
return MIB.addReg(0); return MIB.addReg(0);
} }
static inline
const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB) {
return MIB.addReg(ARM::CPSR);
}
class ARMBaseInstrInfo : public TargetInstrInfoImpl { class ARMBaseInstrInfo : public TargetInstrInfoImpl {
protected: protected:
// Can be only subclassed. // Can be only subclassed.

27
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -133,12 +133,12 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
} }
if (NumBytes <= 255 && NumBytes >= 0) if (NumBytes <= 255 && NumBytes >= 0)
AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
.addImm(NumBytes); .addImm(NumBytes);
else if (NumBytes < 0 && NumBytes >= -255) { else if (NumBytes < 0 && NumBytes >= -255) {
AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
.addImm(NumBytes); .addImm(NumBytes);
AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
.addReg(LdReg, RegState::Kill); .addReg(LdReg, RegState::Kill);
} else } else
MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes); MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes);
@ -148,7 +148,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
MachineInstrBuilder MIB = MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
if (Opc != ARM::tADDhirr) if (Opc != ARM::tADDhirr)
MIB = AddDefaultCC(MIB); MIB = AddDefaultT1CC(MIB);
if (DestReg == ARM::SP || isSub) if (DestReg == ARM::SP || isSub)
MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
else else
@ -254,7 +254,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
Bytes -= ThisVal; Bytes -= ThisVal;
const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
const MachineInstrBuilder MIB = const MachineInstrBuilder MIB =
AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg)); AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg));
AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
} else { } else {
BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
@ -272,7 +272,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
if (isTwoAddr) { if (isTwoAddr) {
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
if (NeedCC) if (NeedCC)
MIB = AddDefaultCC(MIB); MIB = AddDefaultT1CC(MIB);
MIB .addReg(DestReg).addImm(ThisVal); MIB .addReg(DestReg).addImm(ThisVal);
if (NeedPred) if (NeedPred)
MIB = AddDefaultPred(MIB); MIB = AddDefaultPred(MIB);
@ -281,7 +281,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
bool isKill = BaseReg != ARM::SP; bool isKill = BaseReg != ARM::SP;
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
if (NeedCC) if (NeedCC)
MIB = AddDefaultCC(MIB); MIB = AddDefaultT1CC(MIB);
MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal); MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
if (NeedPred) if (NeedPred)
MIB = AddDefaultPred(MIB); MIB = AddDefaultPred(MIB);
@ -302,7 +302,7 @@ void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
if (ExtraOpc) { if (ExtraOpc) {
const TargetInstrDesc &TID = TII.get(ExtraOpc); const TargetInstrDesc &TID = TII.get(ExtraOpc);
AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg)) AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
.addReg(DestReg, RegState::Kill) .addReg(DestReg, RegState::Kill)
.addImm(((unsigned)NumBytes) & 3)); .addImm(((unsigned)NumBytes) & 3));
} }
@ -361,14 +361,14 @@ static void emitThumbConstant(MachineBasicBlock &MBB,
int Chunk = (1 << 8) - 1; int Chunk = (1 << 8) - 1;
int ThisVal = (Imm > Chunk) ? Chunk : Imm; int ThisVal = (Imm > Chunk) ? Chunk : Imm;
Imm -= ThisVal; Imm -= ThisVal;
AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8),
DestReg)) DestReg))
.addImm(ThisVal)); .addImm(ThisVal));
if (Imm > 0) if (Imm > 0)
emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl); emitThumbRegPlusImmediate(MBB, MBBI, DestReg, DestReg, Imm, TII, MRI, dl);
if (isSub) { if (isSub) {
const TargetInstrDesc &TID = TII.get(ARM::tRSB); const TargetInstrDesc &TID = TII.get(ARM::tRSB);
AddDefaultPred(AddDefaultCC(BuildMI(MBB, MBBI, dl, TID, DestReg)) AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg))
.addReg(DestReg, RegState::Kill)); .addReg(DestReg, RegState::Kill));
} }
} }
@ -446,7 +446,8 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (Opcode == ARM::tADDi3) { if (Opcode == ARM::tADDi3) {
removeOperands(MI, i); removeOperands(MI, i);
MachineInstrBuilder MIB(&MI); MachineInstrBuilder MIB(&MI);
AddDefaultPred(AddDefaultCC(MIB).addReg(FrameReg).addImm(Offset/Scale)); AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
.addImm(Offset/Scale));
} else { } else {
MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.getOperand(i).ChangeToRegister(FrameReg, false);
MI.getOperand(i+1).ChangeToImmediate(Offset / Scale); MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);
@ -473,7 +474,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if (Opcode == ARM::tADDi3) { if (Opcode == ARM::tADDi3) {
removeOperands(MI, i); removeOperands(MI, i);
MachineInstrBuilder MIB(&MI); MachineInstrBuilder MIB(&MI);
AddDefaultPred(AddDefaultCC(MIB).addReg(FrameReg).addImm(Mask)); AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg).addImm(Mask));
} else { } else {
MI.getOperand(i).ChangeToRegister(FrameReg, false); MI.getOperand(i).ChangeToRegister(FrameReg, false);
MI.getOperand(i+1).ChangeToImmediate(Mask); MI.getOperand(i+1).ChangeToImmediate(Mask);