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Use TargetOpcode::COPY instead of X86-native register copy instructions when
lowering atomics. This will allow those copies to still be coalesced after TII::isMoveInstr is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108385 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
4bb327d03f
commit
b5378ea12e
@ -7999,7 +7999,6 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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unsigned immOpc,
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unsigned LoadOpc,
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unsigned CXchgOpc,
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unsigned copyOpc,
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unsigned notOpc,
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unsigned EAXreg,
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TargetRegisterClass *RC,
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@ -8076,7 +8075,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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MIB.addReg(tt);
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(*MIB).addOperand(*argOpers[valArgIndx]);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
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MIB.addReg(t1);
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MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
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@ -8087,7 +8086,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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(*MIB).setMemRefs(bInstr->memoperands_begin(),
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bInstr->memoperands_end());
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
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MIB.addReg(EAXreg);
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// insert branch
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@ -8123,7 +8122,6 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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const TargetRegisterClass *RC = X86::GR32RegisterClass;
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const unsigned LoadOpc = X86::MOV32rm;
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const unsigned copyOpc = X86::MOV32rr;
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const unsigned NotOpc = X86::NOT32r;
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const BasicBlock *LLVM_BB = MBB->getBasicBlock();
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@ -8233,14 +8231,14 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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MIB.addReg(t2);
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(*MIB).addOperand(*argOpers[valArgIndx + 1]);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
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MIB.addReg(t1);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
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MIB.addReg(t2);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
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MIB.addReg(t5);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
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MIB.addReg(t6);
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MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
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@ -8251,9 +8249,9 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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(*MIB).setMemRefs(bInstr->memoperands_begin(),
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bInstr->memoperands_end());
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
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MIB.addReg(X86::EAX);
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MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
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MIB.addReg(X86::EDX);
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// insert branch
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@ -8332,12 +8330,12 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
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unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
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if (argOpers[valArgIndx]->isReg())
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MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
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else
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MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
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(*MIB).addOperand(*argOpers[valArgIndx]);
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MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
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MIB.addReg(t1);
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MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
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@ -8359,7 +8357,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
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(*MIB).setMemRefs(mInstr->memoperands_begin(),
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mInstr->memoperands_end());
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MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
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MIB.addReg(X86::EAX);
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// insert branch
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@ -8741,25 +8739,25 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::ATOMAND32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
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X86::AND32ri, X86::MOV32rm,
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X86::LCMPXCHG32, X86::MOV32rr,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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X86::GR32RegisterClass);
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case X86::ATOMOR32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
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X86::OR32ri, X86::MOV32rm,
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X86::LCMPXCHG32, X86::MOV32rr,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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X86::GR32RegisterClass);
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case X86::ATOMXOR32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
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X86::XOR32ri, X86::MOV32rm,
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X86::LCMPXCHG32, X86::MOV32rr,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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X86::GR32RegisterClass);
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case X86::ATOMNAND32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
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X86::AND32ri, X86::MOV32rm,
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X86::LCMPXCHG32, X86::MOV32rr,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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X86::GR32RegisterClass, true);
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case X86::ATOMMIN32:
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@ -8774,25 +8772,25 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::ATOMAND16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
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X86::AND16ri, X86::MOV16rm,
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X86::LCMPXCHG16, X86::MOV16rr,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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X86::GR16RegisterClass);
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case X86::ATOMOR16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
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X86::OR16ri, X86::MOV16rm,
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X86::LCMPXCHG16, X86::MOV16rr,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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X86::GR16RegisterClass);
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case X86::ATOMXOR16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
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X86::XOR16ri, X86::MOV16rm,
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X86::LCMPXCHG16, X86::MOV16rr,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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X86::GR16RegisterClass);
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case X86::ATOMNAND16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
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X86::AND16ri, X86::MOV16rm,
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X86::LCMPXCHG16, X86::MOV16rr,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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X86::GR16RegisterClass, true);
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case X86::ATOMMIN16:
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@ -8807,25 +8805,25 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::ATOMAND8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
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X86::AND8ri, X86::MOV8rm,
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X86::LCMPXCHG8, X86::MOV8rr,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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X86::GR8RegisterClass);
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case X86::ATOMOR8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
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X86::OR8ri, X86::MOV8rm,
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X86::LCMPXCHG8, X86::MOV8rr,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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X86::GR8RegisterClass);
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case X86::ATOMXOR8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
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X86::XOR8ri, X86::MOV8rm,
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X86::LCMPXCHG8, X86::MOV8rr,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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X86::GR8RegisterClass);
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case X86::ATOMNAND8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
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X86::AND8ri, X86::MOV8rm,
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X86::LCMPXCHG8, X86::MOV8rr,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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X86::GR8RegisterClass, true);
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// FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
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@ -8833,25 +8831,25 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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case X86::ATOMAND64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
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X86::AND64ri32, X86::MOV64rm,
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X86::LCMPXCHG64, X86::MOV64rr,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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X86::GR64RegisterClass);
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case X86::ATOMOR64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
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X86::OR64ri32, X86::MOV64rm,
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X86::LCMPXCHG64, X86::MOV64rr,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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X86::GR64RegisterClass);
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case X86::ATOMXOR64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
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X86::XOR64ri32, X86::MOV64rm,
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X86::LCMPXCHG64, X86::MOV64rr,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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X86::GR64RegisterClass);
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case X86::ATOMNAND64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
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X86::AND64ri32, X86::MOV64rm,
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X86::LCMPXCHG64, X86::MOV64rr,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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X86::GR64RegisterClass, true);
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case X86::ATOMMIN64:
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@ -764,7 +764,6 @@ namespace llvm {
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unsigned immOpc,
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unsigned loadOpc,
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unsigned cxchgOpc,
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unsigned copyOpc,
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unsigned notOpc,
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unsigned EAXreg,
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TargetRegisterClass *RC,
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