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Reapply r286080 with a phony change in Hexagon's CMakeLists.txt
Cmake has not recognized that Hexagon.td has a new dependency in HexagonPatterns.td. All changes to that file were not visible to the build bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286084 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
ef6860ffdf
commit
b63144f892
@ -64,3 +64,4 @@ add_subdirectory(AsmParser)
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add_subdirectory(TargetInfo)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(Disassembler)
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@ -112,9 +112,7 @@ public:
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void SelectIntrinsicWOChain(SDNode *N);
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void SelectConstant(SDNode *N);
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void SelectConstantFP(SDNode *N);
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void SelectAdd(SDNode *N);
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void SelectBitcast(SDNode *N);
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void SelectBitOp(SDNode *N);
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// Include the pieces autogenerated from the target description.
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#include "HexagonGenDAGISel.inc"
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@ -888,180 +886,6 @@ void HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
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}
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//
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// Map add followed by a asr -> asr +=.
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//
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void HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
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SDLoc dl(N);
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if (N->getValueType(0) != MVT::i32) {
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SelectCode(N);
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return;
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}
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// Identify nodes of the form: add(asr(...)).
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SDNode* Src1 = N->getOperand(0).getNode();
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if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse() ||
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Src1->getValueType(0) != MVT::i32) {
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SelectCode(N);
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return;
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}
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// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
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// Rd and Rd' are assigned to the same register
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SDNode* Result = CurDAG->getMachineNode(Hexagon::S2_asr_r_r_acc, dl, MVT::i32,
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N->getOperand(1),
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Src1->getOperand(0),
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Src1->getOperand(1));
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ReplaceNode(N, Result);
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}
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//
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// Map the following, where possible.
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// AND/FABS -> clrbit
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// OR -> setbit
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// XOR/FNEG ->toggle_bit.
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//
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void HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
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SDLoc dl(N);
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EVT ValueVT = N->getValueType(0);
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// We handle only 32 and 64-bit bit ops.
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if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
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ValueVT == MVT::f32 || ValueVT == MVT::f64)) {
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SelectCode(N);
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return;
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}
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// We handly only fabs and fneg for V5.
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unsigned Opc = N->getOpcode();
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if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) {
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SelectCode(N);
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return;
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}
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int64_t Val = 0;
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if (Opc != ISD::FABS && Opc != ISD::FNEG) {
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if (N->getOperand(1).getOpcode() == ISD::Constant)
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Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
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else {
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SelectCode(N);
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return;
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}
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}
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if (Opc == ISD::AND) {
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// Check if this is a bit-clearing AND, if not select code the usual way.
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if ((ValueVT == MVT::i32 && isPowerOf2_32(~Val)) ||
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(ValueVT == MVT::i64 && isPowerOf2_64(~Val)))
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Val = ~Val;
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else {
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SelectCode(N);
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return;
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}
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}
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// If OR or AND is being fed by shl, srl and, sra don't do this change,
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// because Hexagon provide |= &= on shl, srl, and sra.
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// Traverse the DAG to see if there is shl, srl and sra.
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if (Opc == ISD::OR || Opc == ISD::AND) {
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switch (N->getOperand(0)->getOpcode()) {
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default:
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break;
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case ISD::SRA:
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case ISD::SRL:
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case ISD::SHL:
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SelectCode(N);
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return;
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}
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}
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// Make sure it's power of 2.
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unsigned BitPos = 0;
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if (Opc != ISD::FABS && Opc != ISD::FNEG) {
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if ((ValueVT == MVT::i32 && !isPowerOf2_32(Val)) ||
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(ValueVT == MVT::i64 && !isPowerOf2_64(Val))) {
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SelectCode(N);
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return;
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}
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// Get the bit position.
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BitPos = countTrailingZeros(uint64_t(Val));
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} else {
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// For fabs and fneg, it's always the 31st bit.
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BitPos = 31;
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}
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unsigned BitOpc = 0;
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// Set the right opcode for bitwise operations.
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switch (Opc) {
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default:
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llvm_unreachable("Only bit-wise/abs/neg operations are allowed.");
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case ISD::AND:
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case ISD::FABS:
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BitOpc = Hexagon::S2_clrbit_i;
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break;
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case ISD::OR:
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BitOpc = Hexagon::S2_setbit_i;
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break;
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case ISD::XOR:
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case ISD::FNEG:
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BitOpc = Hexagon::S2_togglebit_i;
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break;
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}
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SDNode *Result;
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// Get the right SDVal for the opcode.
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SDValue SDVal = CurDAG->getTargetConstant(BitPos, dl, MVT::i32);
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if (ValueVT == MVT::i32 || ValueVT == MVT::f32) {
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Result = CurDAG->getMachineNode(BitOpc, dl, ValueVT,
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N->getOperand(0), SDVal);
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} else {
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// 64-bit gymnastic to use REG_SEQUENCE. But it's worth it.
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EVT SubValueVT;
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if (ValueVT == MVT::i64)
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SubValueVT = MVT::i32;
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else
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SubValueVT = MVT::f32;
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SDNode *Reg = N->getOperand(0).getNode();
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SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID,
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dl, MVT::i64);
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SDValue SubregHiIdx = CurDAG->getTargetConstant(Hexagon::subreg_hireg, dl,
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MVT::i32);
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SDValue SubregLoIdx = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
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MVT::i32);
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SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl,
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MVT::i32, SDValue(Reg, 0));
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SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl,
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MVT::i32, SDValue(Reg, 0));
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// Clear/set/toggle hi or lo registers depending on the bit position.
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if (SubValueVT != MVT::f32 && BitPos < 32) {
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SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
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SubregLO, SDVal);
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const SDValue Ops[] = { RegClass, SubregHI, SubregHiIdx,
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SDValue(Result0, 0), SubregLoIdx };
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Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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dl, ValueVT, Ops);
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} else {
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if (Opc != ISD::FABS && Opc != ISD::FNEG)
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SDVal = CurDAG->getTargetConstant(BitPos-32, dl, MVT::i32);
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SDNode *Result0 = CurDAG->getMachineNode(BitOpc, dl, SubValueVT,
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SubregHI, SDVal);
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const SDValue Ops[] = { RegClass, SDValue(Result0, 0), SubregHiIdx,
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SubregLO, SubregLoIdx };
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Result = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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dl, ValueVT, Ops);
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}
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}
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ReplaceNode(N, Result);
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}
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void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
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MachineFrameInfo &MFI = MF->getFrameInfo();
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const HexagonFrameLowering *HFI = HST->getFrameLowering();
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@ -1127,10 +951,6 @@ void HexagonDAGToDAGISel::Select(SDNode *N) {
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SelectFrameIndex(N);
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return;
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case ISD::ADD:
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SelectAdd(N);
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return;
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case ISD::BITCAST:
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SelectBitcast(N);
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return;
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@ -1151,14 +971,6 @@ void HexagonDAGToDAGISel::Select(SDNode *N) {
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SelectMul(N);
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return;
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::FABS:
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case ISD::FNEG:
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SelectBitOp(N);
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return;
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case ISD::ZERO_EXTEND:
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SelectZeroExtend(N);
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return;
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@ -24,9 +24,34 @@ def IsPow2_32 : PatLeaf<(i32 imm), [{
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return isPowerOf2_32(V);
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}]>;
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def IsPow2_64 : PatLeaf<(i64 imm), [{
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uint64_t V = N->getZExtValue();
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return isPowerOf2_64(V);
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}]>;
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def IsNPow2_32 : PatLeaf<(i32 imm), [{
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uint32_t V = N->getZExtValue();
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return isPowerOf2_32(~V);
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uint32_t NV = ~N->getZExtValue();
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return isPowerOf2_32(NV);
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}]>;
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def IsPow2_64L : PatLeaf<(i64 imm), [{
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uint64_t V = N->getZExtValue();
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return isPowerOf2_64(V) && Log2_64(V) < 32;
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}]>;
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def IsPow2_64H : PatLeaf<(i64 imm), [{
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uint64_t V = N->getZExtValue();
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return isPowerOf2_64(V) && Log2_64(V) >= 32;
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}]>;
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def IsNPow2_64L : PatLeaf<(i64 imm), [{
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uint64_t NV = ~N->getZExtValue();
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return isPowerOf2_64(NV) && Log2_64(NV) < 32;
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}]>;
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def IsNPow2_64H : PatLeaf<(i64 imm), [{
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uint64_t NV = ~N->getZExtValue();
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return isPowerOf2_64(NV) && Log2_64(NV) >= 32;
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}]>;
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def SDEC1 : SDNodeXForm<imm, [{
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@ -36,15 +61,36 @@ def SDEC1 : SDNodeXForm<imm, [{
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def UDEC1 : SDNodeXForm<imm, [{
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uint32_t V = N->getZExtValue();
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assert(V > 0);
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assert(V >= 1);
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return CurDAG->getTargetConstant(V-1, SDLoc(N), MVT::i32);
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}]>;
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def UDEC32 : SDNodeXForm<imm, [{
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uint32_t V = N->getZExtValue();
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assert(V >= 32);
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return CurDAG->getTargetConstant(V-32, SDLoc(N), MVT::i32);
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}]>;
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def Log2_32 : SDNodeXForm<imm, [{
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uint32_t V = N->getZExtValue();
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return CurDAG->getTargetConstant(Log2_32(V), SDLoc(N), MVT::i32);
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}]>;
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def Log2_64 : SDNodeXForm<imm, [{
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uint64_t V = N->getZExtValue();
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return CurDAG->getTargetConstant(Log2_64(V), SDLoc(N), MVT::i32);
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}]>;
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def LogN2_32 : SDNodeXForm<imm, [{
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uint32_t NV = ~N->getZExtValue();
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return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
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}]>;
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def LogN2_64 : SDNodeXForm<imm, [{
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uint64_t NV = ~N->getZExtValue();
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return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32);
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}]>;
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class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
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: Pat<(i1 (OpNode I32:$src1, ImmPred:$src2)),
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@ -528,18 +574,54 @@ def: Pat<(i32 (trunc (ctlz (not I64:$Rss)))), (S2_cl1p I64:$Rss)>;
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// Count trailing ones: 32-bit.
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def: Pat<(cttz (not I32:$Rs)), (S2_ct1 I32:$Rs)>;
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def: Pat<(i32 (and I32:$Rs, (not (shl 1, u5_0ImmPred:$u5)))),
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(S2_clrbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
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def: Pat<(i32 (or I32:$Rs, (shl 1, u5_0ImmPred:$u5))),
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(S2_setbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
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def: Pat<(i32 (xor I32:$Rs, (shl 1, u5_0ImmPred:$u5))),
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(S2_togglebit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
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def: Pat<(i32 (and I32:$Rs, (not (shl 1, I32:$Rt)))),
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(S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(i32 (or I32:$Rs, (shl 1, I32:$Rt))),
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(S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(i32 (xor I32:$Rs, (shl 1, I32:$Rt))),
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(S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
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let AddedComplexity = 20 in { // Complexity greater than and/or/xor
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def: Pat<(and I32:$Rs, IsNPow2_32:$V),
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(S2_clrbit_i IntRegs:$Rs, (LogN2_32 $V))>;
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def: Pat<(or I32:$Rs, IsPow2_32:$V),
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(S2_setbit_i IntRegs:$Rs, (Log2_32 $V))>;
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def: Pat<(xor I32:$Rs, IsPow2_32:$V),
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(S2_togglebit_i IntRegs:$Rs, (Log2_32 $V))>;
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def: Pat<(and I32:$Rs, (not (shl 1, I32:$Rt))),
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(S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(or I32:$Rs, (shl 1, I32:$Rt)),
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(S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
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def: Pat<(xor I32:$Rs, (shl 1, I32:$Rt)),
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(S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
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}
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// Clr/set/toggle bit for 64-bit values with immediate bit index.
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let AddedComplexity = 20 in { // Complexity greater than and/or/xor
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def: Pat<(and I64:$Rss, IsNPow2_64L:$V),
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(REG_SEQUENCE DoubleRegs,
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(i32 (HiReg $Rss)), subreg_hireg,
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(S2_clrbit_i (LoReg $Rss), (LogN2_64 $V)), subreg_loreg)>;
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def: Pat<(and I64:$Rss, IsNPow2_64H:$V),
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(REG_SEQUENCE DoubleRegs,
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(S2_clrbit_i (HiReg $Rss), (UDEC32 (i32 (LogN2_64 $V)))),
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subreg_hireg,
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(i32 (LoReg $Rss)), subreg_loreg)>;
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def: Pat<(or I64:$Rss, IsPow2_64L:$V),
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(REG_SEQUENCE DoubleRegs,
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(i32 (HiReg $Rss)), subreg_hireg,
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(S2_setbit_i (LoReg $Rss), (Log2_64 $V)), subreg_loreg)>;
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def: Pat<(or I64:$Rss, IsPow2_64H:$V),
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(REG_SEQUENCE DoubleRegs,
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(S2_setbit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
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subreg_hireg,
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(i32 (LoReg $Rss)), subreg_loreg)>;
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def: Pat<(xor I64:$Rss, IsPow2_64L:$V),
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(REG_SEQUENCE DoubleRegs,
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(i32 (HiReg $Rss)), subreg_hireg,
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(S2_togglebit_i (LoReg $Rss), (Log2_64 $V)), subreg_loreg)>;
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def: Pat<(xor I64:$Rss, IsPow2_64H:$V),
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(REG_SEQUENCE DoubleRegs,
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(S2_togglebit_i (HiReg $Rss), (UDEC32 (i32 (Log2_64 $V)))),
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subreg_hireg,
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(i32 (LoReg $Rss)), subreg_loreg)>;
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}
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let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
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def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)),
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@ -1642,11 +1724,6 @@ def LogN2_16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
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}]>;
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def LogN2_32 : SDNodeXForm<imm, [{
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uint32_t NV = ~N->getZExtValue();
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return CurDAG->getTargetConstant(Log2_32(NV), SDLoc(N), MVT::i32);
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}]>;
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def NegImm8 : SDNodeXForm<imm, [{
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int8_t NV = -N->getSExtValue();
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return CurDAG->getTargetConstant(NV, SDLoc(N), MVT::i32);
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@ -2615,6 +2692,15 @@ def : Pat <(fneg F32:$src1),
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(S2_togglebit_i F32:$src1, 31)>,
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Requires<[HasV5T]>;
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def: Pat<(fabs F64:$Rs),
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(REG_SEQUENCE DoubleRegs,
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(S2_clrbit_i (HiReg $Rs), 31), subreg_hireg,
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(i32 (LoReg $Rs)), subreg_loreg)>;
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def: Pat<(fneg F64:$Rs),
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(REG_SEQUENCE DoubleRegs,
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(S2_togglebit_i (HiReg $Rs), 31), subreg_hireg,
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(i32 (LoReg $Rs)), subreg_loreg)>;
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def alignedload : PatFrag<(ops node:$addr), (load $addr), [{
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return isAlignedMemNode(dyn_cast<MemSDNode>(N));
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