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[mips] Correct 128-bit shifts on 64-bit targets.

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Summary:
The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now
accounts for both cases.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits, mohit.bhakkad, sagar

Differential Revision: http://reviews.llvm.org/D9337

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236099 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2015-04-29 12:28:58 +00:00
parent 5be17c48fb
commit b6d2c5a952
4 changed files with 17 additions and 17 deletions
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10
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -2074,7 +2074,7 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, DL, MVT::i32));
DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
DAG.getConstant(0, DL, VT), ShiftLeftLo);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
@ -2113,12 +2113,12 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
DL, VT, Hi, Shamt);
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
DAG.getConstant(0x20, DL, MVT::i32));
SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi,
DAG.getConstant(31, DL, VT));
DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
IsSRA ? Shift31 : DAG.getConstant(0, DL, VT), ShiftRightHi);
IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
SDValue Ops[2] = {Lo, Hi};
return DAG.getMergeValues(Ops, DL);

12
test/CodeGen/Mips/llvm-ir/ashr.ll
View File

@ -145,7 +145,7 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
@ -156,7 +156,7 @@ entry:
; M3: $[[BB0]]:
; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: nop
; M3: dsra $2, $4, 31
; M3: dsra $2, $4, 63
; M3: $[[BB1]]:
; M3: jr $ra
; M3: nop
@ -168,18 +168,18 @@ entry:
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrav $2, $4, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31
; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
; 64R6: sll $[[T1:[0-9]+]], $7, 0
; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 32
; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64
; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: dsra $[[T5:[0-9]+]], $4, 31
; 64R6: dsra $[[T5:[0-9]+]], $4, 63
; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; 64R6: or $2, $[[T6]], $[[T4]]
; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7

6
test/CodeGen/Mips/llvm-ir/lshr.ll
View File

@ -139,7 +139,7 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
@ -162,7 +162,7 @@ entry:
; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
; GP64-NOT-R6: dsrlv $2, $4, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $zero, $1
@ -173,7 +173,7 @@ entry:
; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7

6
test/CodeGen/Mips/llvm-ir/shl.ll
View File

@ -151,7 +151,7 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 32
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $2, $[[T1]]
; M3: dsllv $[[T4:[0-9]+]], $4, $7
@ -174,7 +174,7 @@ entry:
; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; GP64-NOT-R6: or $2, $[[T0]], $[[T4]]
; GP64-NOT-R6: dsllv $3, $5, $7
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32
; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $2, $3, $[[T5]]
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $3, $zero, $1
@ -185,7 +185,7 @@ entry:
; 64R6: not $[[T3:[0-9]+]], $[[T2]]
; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]]
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32
; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
; 64R6: dsllv $[[T9:[0-9]+]], $5, $7