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For VLDM/VSTM (Advanced SIMD), set encoding bits Inst{11-8} to 0b1011.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90243 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2009-12-01 17:37:06 +00:00
parent 8f72235a77
commit b731e87649
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMInstrNEON.td
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@ -152,7 +152,7 @@ def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
let Inst{24} = 0; // P bit
let Inst{23} = 1; // U bit
let Inst{20} = 1;
let Inst{11-9} = 0b101;
let Inst{11-8} = 0b1011;
}
// Use vstmia to store a Q register as a D register pair.
@ -164,7 +164,7 @@ def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
let Inst{24} = 0; // P bit
let Inst{23} = 1; // U bit
let Inst{20} = 0;
let Inst{11-9} = 0b101;
let Inst{11-8} = 0b1011;
}
// VLD1 : Vector Load (multiple single elements)