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[Hexagon] Handle spills of partially defined double vector registers
After register allocation it is possible to have a spill of a register that is only partially defined. That in itself it fine, but creates a problem for double vector registers. Stores of such registers are pseudo instructions that are expanded into pairs of individual vector stores, and in case of a partially defined source, one of the stores may use an entirely undefined register. To avoid this, track the defined parts and only generate actual stores for those. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284841 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
dc833052ac
commit
b77f18e769
@ -19,6 +19,7 @@
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#include "HexagonTargetMachine.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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@ -1626,6 +1627,16 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
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if (!MI->getOperand(0).isFI())
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return false;
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// It is possible that the double vector being stored is only partially
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// defined. From the point of view of the liveness tracking, it is ok to
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// store it as a whole, but if we break it up we may end up storing a
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// register that is entirely undefined.
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LivePhysRegs LPR(&HRI);
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LPR.addLiveIns(B);
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SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers;
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for (auto R = B.begin(); R != It; ++R)
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LPR.stepForward(*R, Clobbers);
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DebugLoc DL = MI->getDebugLoc();
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unsigned SrcR = MI->getOperand(2).getReg();
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unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg);
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@ -1642,28 +1653,32 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B,
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unsigned StoreOpc;
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// Store low part.
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if (NeedAlign <= HasAlign)
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StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
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else
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StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
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if (LPR.contains(SrcLo)) {
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if (NeedAlign <= HasAlign)
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StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
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else
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StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
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BuildMI(B, It, DL, HII.get(StoreOpc))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(SrcLo, getKillRegState(IsKill))
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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BuildMI(B, It, DL, HII.get(StoreOpc))
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.addFrameIndex(FI)
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.addImm(0)
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.addReg(SrcLo, getKillRegState(IsKill))
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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}
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// Load high part.
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if (NeedAlign <= MinAlign(HasAlign, Size))
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StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
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else
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StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
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// Store high part.
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if (LPR.contains(SrcHi)) {
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if (NeedAlign <= MinAlign(HasAlign, Size))
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StoreOpc = !Is128B ? Hexagon::V6_vS32b_ai : Hexagon::V6_vS32b_ai_128B;
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else
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StoreOpc = !Is128B ? Hexagon::V6_vS32Ub_ai : Hexagon::V6_vS32Ub_ai_128B;
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BuildMI(B, It, DL, HII.get(StoreOpc))
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.addFrameIndex(FI)
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.addImm(Size)
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.addReg(SrcHi, getKillRegState(IsKill))
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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BuildMI(B, It, DL, HII.get(StoreOpc))
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.addFrameIndex(FI)
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.addImm(Size)
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.addReg(SrcHi, getKillRegState(IsKill))
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.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
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}
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B.erase(It);
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return true;
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95
test/CodeGen/Hexagon/expand-vstorerw-undef.ll
Normal file
95
test/CodeGen/Hexagon/expand-vstorerw-undef.ll
Normal file
@ -0,0 +1,95 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; After register allocation it is possible to have a spill of a register
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; that is only partially defined. That in itself it fine, but creates a
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; problem for double vector registers. Stores of such registers are pseudo
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; instructions that are expanded into pairs of individual vector stores,
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; and in case of a partially defined source, one of the stores may use
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; an entirely undefined register.
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;
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; This testcase used to crash. Make sure we can handle it, and that we
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; do generate a store for the defined part of W0:
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; CHECK-LABEL: fred:
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; CHECK: v[[REG:[0-9]+]] = vsplat
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; CHECK: vmem(r29+#6) = v[[REG]]
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target triple = "hexagon"
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declare void @danny() local_unnamed_addr #0
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declare void @sammy() local_unnamed_addr #0
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declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1
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declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32>, i32) #1
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declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #1
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define hidden void @fred() #2 {
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b0:
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%v1 = load i32, i32* null, align 4
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%v2 = icmp ult i64 0, 2147483648
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br i1 %v2, label %b3, label %b5
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b3: ; preds = %b0
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%v4 = icmp sgt i32 0, -1
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br i1 %v4, label %b6, label %b5
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b5: ; preds = %b3, %b0
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ret void
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b6: ; preds = %b3
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tail call void @danny()
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br label %b7
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b7: ; preds = %b21, %b6
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%v8 = icmp sgt i32 %v1, 0
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%v9 = select i1 %v8, i32 %v1, i32 0
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%v10 = select i1 false, i32 0, i32 %v9
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%v11 = icmp slt i32 %v10, 0
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%v12 = select i1 %v11, i32 %v10, i32 0
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%v13 = icmp slt i32 0, %v12
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br i1 %v13, label %b14, label %b18
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b14: ; preds = %b16, %b7
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br i1 false, label %b15, label %b16
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b15: ; preds = %b14
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br label %b16
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b16: ; preds = %b15, %b14
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%v17 = icmp eq i32 0, %v12
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br i1 %v17, label %b18, label %b14
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b18: ; preds = %b16, %b7
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tail call void @danny()
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%v19 = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 524296) #0
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%v20 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v19, <32 x i32> %v19)
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br label %b22
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b21: ; preds = %b22
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tail call void @sammy() #3
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br label %b7
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b22: ; preds = %b22, %b18
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%v23 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> zeroinitializer, <64 x i32> %v20) #0
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%v24 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v23)
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%v25 = tail call <32 x i32> @llvm.hexagon.V6.vlsrh.128B(<32 x i32> %v24, i32 4) #0
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%v26 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> zeroinitializer, <32 x i32> %v25)
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%v27 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> zeroinitializer) #0
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%v28 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v26) #0
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%v29 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> %v28) #0
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store <32 x i32> %v27, <32 x i32>* null, align 128
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%v30 = add nsw i32 0, 128
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%v31 = getelementptr inbounds i8, i8* null, i32 %v30
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%v32 = bitcast i8* %v31 to <32 x i32>*
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store <32 x i32> %v29, <32 x i32>* %v32, align 128
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%v33 = icmp eq i32 0, 0
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br i1 %v33, label %b21, label %b22
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
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attributes #3 = { nobuiltin nounwind }
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