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[AArch64] Handle vec4, vec8, vec16 *itofp for half
Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235609 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pirama Arumuga Nainar
parent
defaf830f9
commit
b7db5f28c5
@ -557,11 +557,21 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
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// i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
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// -> v8f16 conversions.
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Promote);
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setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Promote);
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// Similarly, there is no direct i32 -> f64 vector conversion instruction.
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
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// Or, direct i32 -> f16 vector conversion. Set it so custom, so the
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// conversion happens in two steps: v4i32 -> v4f32 -> v4f16
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
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// AArch64 doesn't have MUL.2d:
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setOperationAction(ISD::MUL, MVT::v2i64, Expand);
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105
test/CodeGen/AArch64/fp16-v16-instructions.ll
Normal file
105
test/CodeGen/AArch64/fp16-v16-instructions.ll
Normal file
@ -0,0 +1,105 @@
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; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
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; CHECK-LABEL: sitofp_i32:
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; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
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; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
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; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
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; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
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; CHECK-DAG: fcvtn v0.4h, [[S0]]
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; CHECK-DAG: fcvtn v1.4h, [[S2]]
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; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
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; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
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; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
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; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
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%1 = sitofp <16 x i32> %a to <16 x half>
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ret <16 x half> %1
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}
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define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {
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; CHECK-LABEL: sitofp_i64:
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; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: scvtf [[D1:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: scvtf [[D2:v[0-9]+\.2d]], v2.2d
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; CHECK-DAG: scvtf [[D3:v[0-9]+\.2d]], v3.2d
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; CHECK-DAG: scvtf [[D4:v[0-9]+\.2d]], v4.2d
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; CHECK-DAG: scvtf [[D5:v[0-9]+\.2d]], v5.2d
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; CHECK-DAG: scvtf [[D6:v[0-9]+\.2d]], v6.2d
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; CHECK-DAG: scvtf [[D7:v[0-9]+\.2d]], v7.2d
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; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
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; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
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; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
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; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
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; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
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; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
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; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
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; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
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; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
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; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
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; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
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; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
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; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
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; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
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%1 = sitofp <16 x i64> %a to <16 x half>
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ret <16 x half> %1
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}
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define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
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; CHECK-LABEL: uitofp_i32:
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; CHECK-DAG: ucvtf [[S0:v[0-9]+\.4s]], v0.4s
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; CHECK-DAG: ucvtf [[S1:v[0-9]+\.4s]], v1.4s
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; CHECK-DAG: ucvtf [[S2:v[0-9]+\.4s]], v2.4s
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; CHECK-DAG: ucvtf [[S3:v[0-9]+\.4s]], v3.4s
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; CHECK-DAG: fcvtn v0.4h, [[S0]]
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; CHECK-DAG: fcvtn v1.4h, [[S2]]
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; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
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; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
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; CHECK-DAg: ins v0.d[1], v[[R1]].d[0]
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; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
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%1 = uitofp <16 x i32> %a to <16 x half>
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ret <16 x half> %1
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}
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define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {
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; CHECK-LABEL: uitofp_i64:
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; CHECK-DAG: ucvtf [[D0:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: ucvtf [[D1:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: ucvtf [[D2:v[0-9]+\.2d]], v2.2d
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; CHECK-DAG: ucvtf [[D3:v[0-9]+\.2d]], v3.2d
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; CHECK-DAG: ucvtf [[D4:v[0-9]+\.2d]], v4.2d
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; CHECK-DAG: ucvtf [[D5:v[0-9]+\.2d]], v5.2d
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; CHECK-DAG: ucvtf [[D6:v[0-9]+\.2d]], v6.2d
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; CHECK-DAG: ucvtf [[D7:v[0-9]+\.2d]], v7.2d
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; CHECK-DAG: fcvtn [[S0:v[0-9]+]].2s, [[D0]]
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; CHECK-DAG: fcvtn [[S1:v[0-9]+]].2s, [[D2]]
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; CHECK-DAG: fcvtn [[S2:v[0-9]+]].2s, [[D4]]
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; CHECK-DAG: fcvtn [[S3:v[0-9]+]].2s, [[D6]]
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; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
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; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
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; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
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; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
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; CHECK-DAG: fcvtn v0.4h, [[S0]].4s
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; CHECK-DAG: fcvtn v1.4h, [[S2]].4s
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; CHECK-DAG: fcvtn v[[R1:[0-9]+]].4h, [[S1]].4s
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; CHECK-DAG: fcvtn v[[R3:[0-9]+]].4h, [[S3]].4s
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; CHECK-DAG: ins v0.d[1], v[[R1]].d[0]
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; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
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%1 = uitofp <16 x i64> %a to <16 x half>
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ret <16 x half> %1
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}
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attributes #0 = { nounwind }
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
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define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
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entry:
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@ -129,3 +129,93 @@ define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
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%2 = bitcast <4 x half> %a to <4 x i16>
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ret <4 x i16> %2
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}
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define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: sitofp_i8:
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; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
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; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
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; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
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; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
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; CHECK-NEXT: ret
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%1 = sitofp <4 x i8> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
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; CHECK-LABEL: sitofp_i16:
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; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
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; CHECK-NEXT: ret
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%1 = sitofp <4 x i16> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: sitofp_i32:
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; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
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; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
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%1 = sitofp <4 x i32> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
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; CHECK-LABEL: sitofp_i64:
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; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
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; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
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%1 = sitofp <4 x i64> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
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; CHECK-LABEL: uitofp_i8:
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; CHECK-NEXT: bic v0.4h, #0xff, lsl #8
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; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
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; CHECK-NEXT: ret
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%1 = uitofp <4 x i8> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
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; CHECK-LABEL: uitofp_i16:
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; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
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; CHECK-NEXT: ret
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%1 = uitofp <4 x i16> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
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; CHECK-LABEL: uitofp_i32:
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; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
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; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
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%1 = uitofp <4 x i32> %a to <4 x half>
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ret <4 x half> %1
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}
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define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
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; CHECK-LABEL: uitofp_i64:
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; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
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; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
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; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
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%1 = uitofp <4 x i64> %a to <4 x half>
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ret <4 x half> %1
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}
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attributes #0 = { nounwind }
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
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define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) {
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entry:
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@ -253,3 +253,109 @@ define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) {
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ret <8 x i16> %2
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}
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define <8 x half> @sitofp_i8(<8 x i8> %a) #0 {
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; CHECK-LABEL: sitofp_i8:
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; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0
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; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
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; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
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; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
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; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
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; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
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; CHECK-DAG: fcvtn v0.4h, [[HIF]]
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; CHECK: ins v0.d[1], v[[LOREG]].d[0]
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%1 = sitofp <8 x i8> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
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; CHECK-LABEL: sitofp_i16:
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; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
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; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v0.4h, #0
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; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]]
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; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]]
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; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
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; CHECK-DAG: fcvtn v0.4h, [[HIF]]
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; CHECK: ins v0.d[1], v[[LOREG]].d[0]
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%1 = sitofp <8 x i16> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
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; CHECK-LABEL: sitofp_i32:
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; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
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; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s
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; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
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; CHECK-DAG: fcvtn v0.4h, [[OP1]]
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; CHECK: ins v0.d[1], v[[REG]].d[0]
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%1 = sitofp <8 x i32> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {
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; CHECK-LABEL: sitofp_i64:
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; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
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; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
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; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
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; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
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; CHECK: fcvtn v0.4h, [[OP3]].4s
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%1 = sitofp <8 x i64> %a to <8 x half>
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ret <8 x half> %1
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}
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define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
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; CHECK-LABEL: uitofp_i8:
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; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
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; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
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; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
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; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
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; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
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; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
|
||||
; CHECK-DAG: fcvtn v0.4h, [[HIF]]
|
||||
; CHECK: ins v0.d[1], v[[LOREG]].d[0]
|
||||
%1 = uitofp <8 x i8> %a to <8 x half>
|
||||
ret <8 x half> %1
|
||||
}
|
||||
|
||||
|
||||
define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
|
||||
; CHECK-LABEL: uitofp_i16:
|
||||
; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
|
||||
; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0
|
||||
; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]]
|
||||
; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]]
|
||||
; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]]
|
||||
; CHECK-DAG: fcvtn v0.4h, [[HIF]]
|
||||
; CHECK: ins v0.d[1], v[[LOREG]].d[0]
|
||||
%1 = uitofp <8 x i16> %a to <8 x half>
|
||||
ret <8 x half> %1
|
||||
}
|
||||
|
||||
|
||||
define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
|
||||
; CHECK-LABEL: uitofp_i32:
|
||||
; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
|
||||
; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s
|
||||
; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]]
|
||||
; CHECK-DAG: fcvtn v0.4h, [[OP1]]
|
||||
; CHECK: ins v0.d[1], v[[REG]].d[0]
|
||||
%1 = uitofp <8 x i32> %a to <8 x half>
|
||||
ret <8 x half> %1
|
||||
}
|
||||
|
||||
|
||||
define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {
|
||||
; CHECK-LABEL: uitofp_i64:
|
||||
; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
|
||||
; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
|
||||
; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
|
||||
; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
|
||||
; CHECK: fcvtn v0.4h, [[OP3]].4s
|
||||
%1 = uitofp <8 x i64> %a to <8 x half>
|
||||
ret <8 x half> %1
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user