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R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()

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Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO,
VCC_HI, and M0.  The previous implementation would assertion fail
when passed these registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218349 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-09-24 01:33:22 +00:00
parent 860cabe1e6
commit b8112412cf
1 changed files with 10 additions and 1 deletions
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11
lib/Target/R600/SIRegisterInfo.cpp
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@ -343,7 +343,6 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
case 1: return AMDGPU::VCC_HI;
default: llvm_unreachable("Invalid SubIdx for VCC");
}
break;
case AMDGPU::FLAT_SCR:
switch (Channel) {
@ -368,6 +367,16 @@ unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
break;
}
const TargetRegisterClass *RC = getPhysRegClass(Reg);
// 32-bit registers don't have sub-registers, so we can just return the
// Reg. We need to have this check here, because the calculation below
// using getHWRegIndex() will fail with special 32-bit registers like
// VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
if (RC->getSize() == 4) {
assert(Channel == 0);
return Reg;
}
unsigned Index = getHWRegIndex(Reg);
return SubRC->getRegister(Index + Channel);
}