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Add support for using non-pic code for arm and thumb1 when emitting the sjlj

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dispatch code.  As far as I can tell the thumb2 code is behaving as expected.
I was able to compile and run the associated test case for both arm and thumb1.
rdar://13066352


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176363 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2013-03-01 18:30:38 +00:00
parent 5f58358c90
commit b8f307b2d6
2 changed files with 110 additions and 10 deletions
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31
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -6332,6 +6332,7 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
unsigned MJTI = JTI->createJumpTableIndex(LPadList);
unsigned UId = AFI->createJumpTableUId();
Reloc::Model RelocM = getTargetMachine().getRelocationModel();
// Create the MBBs for the dispatch code.
@ -6492,11 +6493,14 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
.addImm(0)
.addMemOperand(JTMMOLd));
unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
.addReg(ARM::CPSR, RegState::Define)
.addReg(NewVReg5, RegState::Kill)
.addReg(NewVReg3));
unsigned NewVReg6 = NewVReg5;
if (RelocM == Reloc::PIC_) {
NewVReg6 = MRI->createVirtualRegister(TRC);
AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
.addReg(ARM::CPSR, RegState::Define)
.addReg(NewVReg5, RegState::Kill)
.addReg(NewVReg3));
}
BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
.addReg(NewVReg6, RegState::Kill)
@ -6576,11 +6580,18 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
.addImm(0)
.addMemOperand(JTMMOLd));
BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
.addReg(NewVReg5, RegState::Kill)
.addReg(NewVReg4)
.addJumpTableIndex(MJTI)
.addImm(UId);
if (RelocM == Reloc::PIC_) {
BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
.addReg(NewVReg5, RegState::Kill)
.addReg(NewVReg4)
.addJumpTableIndex(MJTI)
.addImm(UId);
} else {
BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
.addReg(NewVReg5, RegState::Kill)
.addJumpTableIndex(MJTI)
.addImm(UId);
}
}
// Add the jump table entries as successors to the MBB.

89
test/CodeGen/ARM/eh-dispcont.ll Normal file
View File

@ -0,0 +1,89 @@
; RUN: llc -mtriple armv7-apple-ios -relocation-model=pic -o - %s | FileCheck %s -check-prefix=ARM-PIC
; RUN: llc -mtriple armv7-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=ARM-NOPIC
; RUN: llc -mtriple armv7-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=ARM-NOPIC
; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=pic -o - %s | FileCheck %s -check-prefix=THUMB1-PIC
; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=static -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC
; RUN: llc -mtriple thumbv6-apple-ios -relocation-model=dynamic-no-pic -o - %s | FileCheck %s -check-prefix=THUMB1-NOPIC
@_ZTIi = external constant i8*
define i32 @main() #0 {
entry:
%exception = tail call i8* @__cxa_allocate_exception(i32 4) #1
%0 = bitcast i8* %exception to i32*
store i32 1, i32* %0, align 4
invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #2
to label %unreachable unwind label %lpad
lpad: ; preds = %entry
%1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*)
catch i8* null
%2 = extractvalue { i8*, i32 } %1, 0
%3 = tail call i8* @__cxa_begin_catch(i8* %2) #1
tail call void @__cxa_end_catch()
ret i32 0
unreachable: ; preds = %entry
unreachable
}
declare i8* @__cxa_allocate_exception(i32)
declare void @__cxa_throw(i8*, i8*, i8*)
declare i8* @__cxa_begin_catch(i8*)
declare void @__cxa_end_catch()
declare i32 @__gxx_personality_sj0(...)
attributes #0 = { ssp }
attributes #1 = { nounwind }
attributes #2 = { noreturn }
; ARM-PIC: cxa_throw
; ARM-PIC: trap
; ARM-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
; ARM-PIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
; ARM-PIC: add pc, [[REG0]], [[REG1]]
; ARM-PIC: [[LJTI]]
; ARM-PIC: .data_region jt32
; ARM-PIC: .long [[LABEL:LBB0_[0-9]]]-[[LJTI]]
; ARM-PIC: .end_data_region
; ARM-PIC: [[LABEL]]
; ARM-NOPIC: cxa_throw
; ARM-NOPIC: trap
; ARM-NOPIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
; ARM-NOPIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
; ARM-NOPIC: mov pc, [[REG0]]
; ARM-NOPIC: [[LJTI]]
; ARM-NOPIC: .data_region jt32
; ARM-NOPIC: .long [[LABEL:LBB0_[0-9]]]
; ARM-NOPIC: .end_data_region
; ARM-NOPIC: [[LABEL]]
; THUMB1-PIC: cxa_throw
; THUMB1-PIC: trap
; THUMB1-PIC: adr [[REG0:r[0-9]+]], [[LJTI:.*]]
; THUMB1-PIC: adds [[REG1:r[0-9]+]], [[REG1]], [[REG0]]
; THUMB1-PIC: ldr [[REG1]]
; THUMB1-PIC: adds [[REG0]], [[REG1]], [[REG0]]
; THUMB1-PIC: mov pc, [[REG0]]
; THUMB1-PIC: [[LJTI]]
; THUMB1-PIC: .data_region jt32
; THUMB1-PIC: .long [[LABEL:LBB0_[0-9]]]-[[LJTI]]
; THUMB1-PIC: .end_data_region
; THUMB1-PIC: [[LABEL]]
; THUMB1-NOPIC: cxa_throw
; THUMB1-NOPIC: trap
; THUMB1-NOPIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
; THUMB1-NOPIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
; THUMB1-NOPIC: ldr [[REG0]]
; THUMB1-NOPIC: mov pc, [[REG0]]
; THUMB1-NOPIC: [[LJTI]]
; THUMB1-NOPIC: .data_region jt32
; THUMB1-NOPIC: .long [[LABEL:LBB0_[0-9]]]+1
; THUMB1-NOPIC: .end_data_region
; THUMB1-NOPIC: [[LABEL]]