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Use Evan's outflag stuff to implement V8cmpicc. This allows us to write a

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pattern for SUBCCrr, and makes it trivial to add support for SUBCCri, eliminating
an instruction in the common "setcc X, imm" case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25212 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-11 07:49:38 +00:00
parent 3fbb726141
commit b9169ceb23
4 changed files with 54 additions and 32 deletions
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32
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -635,10 +635,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Get the condition flag. // Get the condition flag.
if (LHS.getValueType() == MVT::i32) { if (LHS.getValueType() == MVT::i32) {
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops);
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
} else { } else {
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops);
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
} }
} }
@ -651,7 +663,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
unsigned Opc; unsigned Opc;
Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); std::vector<MVT::ValueType> VTs;
VTs.push_back(LHS.getValueType());
VTs.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand CompareFlag = DAG.getNode(Opc, VTs, Ops).getValue(1);
Opc = LHS.getValueType() == MVT::i32 ? Opc = LHS.getValueType() == MVT::i32 ?
V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
@ -883,14 +901,6 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
CurDAG->getTargetFrameIndex(FI, MVT::i32), CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32)); CurDAG->getTargetConstant(0, MVT::i32));
} }
case V8ISD::CMPICC: {
// FIXME: Handle compare with immediate.
SDOperand LHS = Select(N->getOperand(0));
SDOperand RHS = Select(N->getOperand(1));
SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
LHS, RHS);
return CodeGenMap[Op] = Result.getValue(1);
}
case ISD::ADD_PARTS: { case ISD::ADD_PARTS: {
SDOperand LHSL = Select(N->getOperand(0)); SDOperand LHSL = Select(N->getOperand(0));
SDOperand LHSH = Select(N->getOperand(1)); SDOperand LHSH = Select(N->getOperand(1));

11
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -59,8 +59,6 @@ def MEMri : Operand<i32> {
def brtarget : Operand<OtherVT>; def brtarget : Operand<OtherVT>;
def calltarget : Operand<i32>; def calltarget : Operand<i32>;
def SDTV8cmpicc :
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
def SDTV8cmpfcc : def SDTV8cmpfcc :
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
def SDTV8brcc : def SDTV8brcc :
@ -74,7 +72,8 @@ SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
def SDTV8ITOF : def SDTV8ITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp,
[SDNPCommutative, SDNPOutFlag]>;
def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
@ -405,10 +404,12 @@ def SUBXri : F3_2<2, 0b001100,
"subx $b, $c, $dst", []>; "subx $b, $c, $dst", []>;
def SUBCCrr : F3_1<2, 0b010100, def SUBCCrr : F3_1<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subcc $b, $c, $dst", []>; "subcc $b, $c, $dst",
[(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
def SUBCCri : F3_2<2, 0b010100, def SUBCCri : F3_2<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c), (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"subcc $b, $c, $dst", []>; "subcc $b, $c, $dst",
[(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
def SUBXCCrr: F3_1<2, 0b011100, def SUBXCCrr: F3_1<2, 0b011100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subxcc $b, $c, $dst", []>; "subxcc $b, $c, $dst", []>;

32
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -635,10 +635,22 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Get the condition flag. // Get the condition flag.
if (LHS.getValueType() == MVT::i32) { if (LHS.getValueType() == MVT::i32) {
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops);
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
} else { } else {
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops);
return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
} }
} }
@ -651,7 +663,13 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
unsigned Opc; unsigned Opc;
Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); std::vector<MVT::ValueType> VTs;
VTs.push_back(LHS.getValueType());
VTs.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(LHS);
Ops.push_back(RHS);
SDOperand CompareFlag = DAG.getNode(Opc, VTs, Ops).getValue(1);
Opc = LHS.getValueType() == MVT::i32 ? Opc = LHS.getValueType() == MVT::i32 ?
V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
@ -883,14 +901,6 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
CurDAG->getTargetFrameIndex(FI, MVT::i32), CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32)); CurDAG->getTargetConstant(0, MVT::i32));
} }
case V8ISD::CMPICC: {
// FIXME: Handle compare with immediate.
SDOperand LHS = Select(N->getOperand(0));
SDOperand RHS = Select(N->getOperand(1));
SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
LHS, RHS);
return CodeGenMap[Op] = Result.getValue(1);
}
case ISD::ADD_PARTS: { case ISD::ADD_PARTS: {
SDOperand LHSL = Select(N->getOperand(0)); SDOperand LHSL = Select(N->getOperand(0));
SDOperand LHSH = Select(N->getOperand(1)); SDOperand LHSH = Select(N->getOperand(1));

11
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -59,8 +59,6 @@ def MEMri : Operand<i32> {
def brtarget : Operand<OtherVT>; def brtarget : Operand<OtherVT>;
def calltarget : Operand<i32>; def calltarget : Operand<i32>;
def SDTV8cmpicc :
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
def SDTV8cmpfcc : def SDTV8cmpfcc :
SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>; SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
def SDTV8brcc : def SDTV8brcc :
@ -74,7 +72,8 @@ SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
def SDTV8ITOF : def SDTV8ITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>; def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp,
[SDNPCommutative, SDNPOutFlag]>;
def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>; def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>; def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>; def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
@ -405,10 +404,12 @@ def SUBXri : F3_2<2, 0b001100,
"subx $b, $c, $dst", []>; "subx $b, $c, $dst", []>;
def SUBCCrr : F3_1<2, 0b010100, def SUBCCrr : F3_1<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subcc $b, $c, $dst", []>; "subcc $b, $c, $dst",
[(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
def SUBCCri : F3_2<2, 0b010100, def SUBCCri : F3_2<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c), (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"subcc $b, $c, $dst", []>; "subcc $b, $c, $dst",
[(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
def SUBXCCrr: F3_1<2, 0b011100, def SUBXCCrr: F3_1<2, 0b011100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subxcc $b, $c, $dst", []>; "subxcc $b, $c, $dst", []>;