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[RDF] Use RegisterId typedef more consistently, NFC

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284857 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek 2016-10-21 19:12:13 +00:00
parent 79f85df65a
commit b96d4379cf
3 changed files with 12 additions and 11 deletions
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16
lib/Target/Hexagon/RDFGraph.cpp
View File

@ -630,7 +630,7 @@ bool TargetOperandInfo::isFixedReg(const MachineInstr &In, unsigned OpNum)
// uses or defs, and those lists do not allow sub-registers.
if (Op.getSubReg() != 0)
return false;
uint32_t Reg = Op.getReg();
RegisterId Reg = Op.getReg();
const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
: D.getImplicitUses();
if (!ImpR)
@ -643,7 +643,7 @@ bool TargetOperandInfo::isFixedReg(const MachineInstr &In, unsigned OpNum)
RegisterRef RegisterAggr::normalize(RegisterRef RR) const {
uint32_t SuperReg = RR.Reg;
RegisterId SuperReg = RR.Reg;
while (true) {
MCSuperRegIterator SR(SuperReg, &TRI, false);
if (!SR.isValid())
@ -706,7 +706,7 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
}
RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) {
for (std::pair<uint32_t,LaneBitmask> P : RG.Masks)
for (std::pair<RegisterId,LaneBitmask> P : RG.Masks)
insert(RegisterRef(P.first, P.second));
return *this;
}
@ -725,7 +725,7 @@ RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
}
RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) {
for (std::pair<uint32_t,LaneBitmask> P : RG.Masks)
for (std::pair<RegisterId,LaneBitmask> P : RG.Masks)
clear(RegisterRef(P.first, P.second));
return *this;
}
@ -850,7 +850,7 @@ unsigned DataFlowGraph::DefStack::nextDown(unsigned P) const {
// Register information.
// Get the list of references aliased to RR. Lane masks are ignored.
RegisterSet DataFlowGraph::getAliasSet(uint32_t Reg) const {
RegisterSet DataFlowGraph::getAliasSet(RegisterId Reg) const {
// Do not include RR in the alias set.
RegisterSet AS;
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
@ -866,9 +866,9 @@ RegisterSet DataFlowGraph::getLandingPadLiveIns() const {
const Constant *PF = F.hasPersonalityFn() ? F.getPersonalityFn()
: nullptr;
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
if (uint32_t R = TLI.getExceptionPointerRegister(PF))
if (RegisterId R = TLI.getExceptionPointerRegister(PF))
LR.insert(RegisterRef(R));
if (uint32_t R = TLI.getExceptionSelectorRegister(PF))
if (RegisterId R = TLI.getExceptionSelectorRegister(PF))
LR.insert(RegisterRef(R));
return LR;
}
@ -1072,7 +1072,7 @@ RegisterRef DataFlowGraph::makeRegRef(unsigned Reg, unsigned Sub) const {
RegisterRef DataFlowGraph::normalizeRef(RegisterRef RR) const {
// FIXME copied from RegisterAggr
uint32_t SuperReg = RR.Reg;
RegisterId SuperReg = RR.Reg;
while (true) {
MCSuperRegIterator SR(SuperReg, &TRI, false);
if (!SR.isValid())

4
lib/Target/Hexagon/RDFGraph.h
View File

@ -790,7 +790,7 @@ namespace rdf {
// Make this std::unordered_map for speed of accessing elements.
// Map: Register (physical or virtual) -> DefStack
typedef std::unordered_map<uint32_t,DefStack> DefStackMap;
typedef std::unordered_map<RegisterId,DefStack> DefStackMap;
void build(unsigned Options = BuildOptions::None);
void pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM);
@ -863,7 +863,7 @@ namespace rdf {
private:
void reset();
RegisterSet getAliasSet(uint32_t Reg) const;
RegisterSet getAliasSet(RegisterId Reg) const;
RegisterSet getLandingPadLiveIns() const;
NodeAddr<NodeBase*> newNode(uint16_t Attrs);

3
lib/Target/Hexagon/RDFLiveness.h
View File

@ -103,7 +103,8 @@ namespace rdf {
// Phi information:
//
// map: NodeId -> (map: RegisterRef -> NodeSet)
// RealUseMap
// map: NodeId -> (map: RegisterId -> NodeRefSet)
// phi id -> (map: register -> set of reached non-phi uses)
std::map<NodeId, RefMap> RealUseMap;