[Thumb1] Move padding earlier when synthesizing TBBs off of the PC

When the base register (register pointing to the jump table) is the PC, we expect the jump table to directly follow the jump sequence with no intervening padding.

If there is intervening padding, the calculated offsets will not be correct. One solution would be to account for any padding in the emitted LDRB instruction, but at the moment we don't support emitting MCExprs for the load offset.

In the meantime, it's correct and only a slight amount worse to just move the padding up, from just before the jump table to just before the jump instruction sequence. We can do that by emitting code alignment before the jump sequence, as we know the number of instructions in the sequence is always 4.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286107 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMAsmPrinter.cpp

@@ -1741,6 +1741,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
       //    LSLS idx, #1
       //    ADDS pc, pc, idx
 
+      // When using PC as the base, it's important that there is no padding
+      // between the last ADDS and the start of the jump table. The jump table
+      // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
+      //
+      // FIXME: Ideally we could vary the LDRB index based on the padding
+      // between the sequence and jump table, however that relies on MCExprs
+      // for load indexes which are currently not supported.
+      OutStreamer->EmitCodeAlignment(4);
       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
                                        .addReg(Idx)
                                        .addReg(Idx)

test/CodeGen/ARM/arm-position-independence-jump-table.ll

@@ -85,7 +85,7 @@ lab4:
 ; THUMB2: [[LBB4]]
 ; THUMB2-NEXT: b exit4
 
-
+; THUMB1: .p2align 2
 ; THUMB1: add     r[[x:[0-9]+]], pc
 ; THUMB1: ldrb    r[[x]], [r[[x]], #4]
 ; THUMB1: lsls    r[[x]], r[[x]], #1