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remove some uses of MachineOpCode, move getSchedClass

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into TargetInstrDescriptor from TargetInstrInfo.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45678 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-01-07 02:46:03 +00:00
parent 8ca5c67c6e
commit ba6da5d5b7
2 changed files with 22 additions and 22 deletions
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39
include/llvm/Target/TargetInstrInfo.h
View File

@ -37,7 +37,6 @@ template<class T> class SmallVectorImpl;
//===----------------------------------------------------------------------===//
typedef short MachineOpCode;
typedef unsigned InstrSchedClass;
//===----------------------------------------------------------------------===//
// struct TargetInstrDescriptor:
@ -175,11 +174,11 @@ public:
class TargetInstrDescriptor {
public:
MachineOpCode Opcode; // The opcode.
unsigned short Opcode; // The opcode.
unsigned short numOperands; // Num of args (may be more if variable_ops).
unsigned short numDefs; // Num of args that are definitions.
const char * Name; // Assembly language mnemonic for the opcode.
InstrSchedClass schedClass; // enum identifying instr sched class
unsigned SchedClass; // enum identifying instr sched class
unsigned Flags; // flags identifying machine instr class
unsigned TSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr
@ -259,6 +258,10 @@ public:
bool hasDelaySlot() const {
return Flags & M_DELAY_SLOT_FLAG;
}
unsigned getSchedClass() const {
return SchedClass;
}
};
@ -291,32 +294,28 @@ public:
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const TargetInstrDescriptor& get(MachineOpCode Opcode) const {
assert((unsigned)Opcode < NumOpcodes);
const TargetInstrDescriptor& get(unsigned Opcode) const {
assert(Opcode < NumOpcodes);
return desc[Opcode];
}
const char *getName(MachineOpCode Opcode) const {
const char *getName(unsigned Opcode) const {
return get(Opcode).Name;
}
int getNumOperands(MachineOpCode Opcode) const {
int getNumOperands(unsigned Opcode) const {
return get(Opcode).numOperands;
}
int getNumDefs(MachineOpCode Opcode) const {
int getNumDefs(unsigned Opcode) const {
return get(Opcode).numDefs;
}
InstrSchedClass getSchedClass(MachineOpCode Opcode) const {
return get(Opcode).schedClass;
}
const unsigned *getImplicitUses(MachineOpCode Opcode) const {
const unsigned *getImplicitUses(unsigned Opcode) const {
return get(Opcode).ImplicitUses;
}
const unsigned *getImplicitDefs(MachineOpCode Opcode) const {
const unsigned *getImplicitDefs(unsigned Opcode) const {
return get(Opcode).ImplicitDefs;
}
@ -325,26 +324,26 @@ public:
// Query instruction class flags according to the machine-independent
// flags listed above.
//
bool isReturn(MachineOpCode Opcode) const {
bool isReturn(unsigned Opcode) const {
return get(Opcode).Flags & M_RET_FLAG;
}
bool isCommutableInstr(MachineOpCode Opcode) const {
bool isCommutableInstr(unsigned Opcode) const {
return get(Opcode).Flags & M_COMMUTABLE;
}
/// usesCustomDAGSchedInsertionHook - Return true if this instruction requires
/// custom insertion support when the DAG scheduler is inserting it into a
/// machine basic block.
bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const {
bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const {
return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
}
bool hasVariableOperands(MachineOpCode Opcode) const {
bool hasVariableOperands(unsigned Opcode) const {
return get(Opcode).Flags & M_VARIABLE_OPS;
}
bool hasOptionalDef(MachineOpCode Opcode) const {
bool hasOptionalDef(unsigned Opcode) const {
return get(Opcode).Flags & M_HAS_OPTIONAL_DEF;
}
@ -390,7 +389,7 @@ protected:
public:
/// getOperandConstraint - Returns the value of the specific constraint if
/// it is set. Returns -1 if it is not set.
int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
int getOperandConstraint(unsigned Opcode, unsigned OpNum,
TOI::OperandConstraint Constraint) const {
return get(Opcode).getOperandConstraint(OpNum, Constraint);
}

5
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -207,7 +207,8 @@ void ScheduleDAG::ComputeLatency(SUnit *SU) {
} else {
SU->Latency = 0;
if (SU->Node->isTargetOpcode()) {
unsigned SchedClass = TII->getSchedClass(SU->Node->getTargetOpcode());
unsigned SchedClass =
TII->get(SU->Node->getTargetOpcode()).getSchedClass();
InstrStage *S = InstrItins.begin(SchedClass);
InstrStage *E = InstrItins.end(SchedClass);
for (; S != E; ++S)
@ -216,7 +217,7 @@ void ScheduleDAG::ComputeLatency(SUnit *SU) {
for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
SDNode *FNode = SU->FlaggedNodes[i];
if (FNode->isTargetOpcode()) {
unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
InstrStage *S = InstrItins.begin(SchedClass);
InstrStage *E = InstrItins.end(SchedClass);
for (; S != E; ++S)