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Fix gcc warning of different enum and non-enum types in ternary

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Make '0' literal explicitly unsigned with '0u'.
This appeared after r236775.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236838 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Denis Protivensky 2015-05-08 12:21:03 +00:00
parent 3fdd82e066
commit baac106e1d
1 changed files with 8 additions and 8 deletions
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16
lib/Target/X86/X86ISelLowering.cpp
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@ -20942,16 +20942,16 @@ matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
default: break;
case ISD::SETULT:
case ISD::SETULE:
Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
case ISD::SETUGT:
case ISD::SETUGE:
Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
case ISD::SETLT:
case ISD::SETLE:
Opc = hasSigned ? X86ISD::SMIN : 0; break;
Opc = hasSigned ? X86ISD::SMIN : 0u; break;
case ISD::SETGT:
case ISD::SETGE:
Opc = hasSigned ? X86ISD::SMAX : 0; break;
Opc = hasSigned ? X86ISD::SMAX : 0u; break;
}
// Check for x CC y ? y : x -- a min/max with reversed arms.
} else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
@ -20960,16 +20960,16 @@ matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
default: break;
case ISD::SETULT:
case ISD::SETULE:
Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
case ISD::SETUGT:
case ISD::SETUGE:
Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
case ISD::SETLT:
case ISD::SETLE:
Opc = hasSigned ? X86ISD::SMAX : 0; break;
Opc = hasSigned ? X86ISD::SMAX : 0u; break;
case ISD::SETGT:
case ISD::SETGE:
Opc = hasSigned ? X86ISD::SMIN : 0; break;
Opc = hasSigned ? X86ISD::SMIN : 0u; break;
}
}