RPCSX/llvm
1
0
Fork 0
mirror of https://github.com/RPCSX/llvm.git synced 2024-12-03 17:31:50 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Revert 84843. Evan, this was breaking some of the if-conversion tests.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84868 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-22 16:52:21 +00:00
parent 09b5d90429
commit bac6ed4ba4
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -103,16 +103,18 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createARMLoadStoreOptimizationPass());
PM.add(createIfConverterPass());
}
return true;
}
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
PM.add(createIfConverterPass());
if (Subtarget.isThumb2()) {
PM.add(createThumb2ITBlockPass());
PM.add(createThumb2SizeReductionPass());

3
test/CodeGen/ARM/ifcvt5.ll
View File

@ -11,8 +11,7 @@ entry:
define void @t1(i32 %a, i32 %b) {
; CHECK: t1:
; CHECK: movge
; CHECK: blge _foo
; CHECK: ldmltfd sp!, {r7, pc}
entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock