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Fixed a bug when trying to optimize a extract vector element of a

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bit convert that changes the number of elements of a shuffle.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60829 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2008-12-10 03:59:02 +00:00
parent 5788d1a169
commit bae527d949
2 changed files with 15 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -4874,7 +4874,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
MVT LVT = EVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
MVT BCVT = InVec.getOperand(0).getValueType();
if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()) ||
VT.getVectorNumElements() != BCVT.getVectorNumElements())
return SDValue();
InVec = InVec.getOperand(0);
EVT = BCVT.getVectorElementType();

13
test/CodeGen/X86/extractelement-shuffle.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llvm-as < %s | llc
; Examples that exhibits a bug in DAGCombine. The case is triggered by the
; following program. The bug is DAGCombine assumes that the bit convert
; preserves the number of elements so the optimization code tries to read
; through the 3rd mask element, which doesn't exist.
define i32 @update(<2 x i64> %val1, <2 x i64> %val2) nounwind readnone {
entry:
%shuf = shufflevector <2 x i64> %val1, <2 x i64> %val2, <2 x i32> <i32 0, i32 3>;
%bit = bitcast <2 x i64> %shuf to <4 x i32>;
%res = extractelement <4 x i32> %bit, i32 3;
ret i32 %res;
}