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Don't assert on 'select_cc SETUO'

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25423 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-18 19:42:35 +00:00
parent c16257f053
commit bc38dbfd9b
1 changed files with 2 additions and 2 deletions
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4
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -238,7 +238,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// subtraction at all. // subtraction at all.
if (isFloatingPointZero(RHS)) if (isFloatingPointZero(RHS))
switch (CC) { switch (CC) {
default: assert(0 && "Invalid FSEL condition"); abort(); default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT: case ISD::SETULT:
case ISD::SETLT: case ISD::SETLT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
@ -260,7 +260,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
SDOperand Cmp; SDOperand Cmp;
switch (CC) { switch (CC) {
default: assert(0 && "Invalid FSEL condition"); abort(); default: break; // SETUO etc aren't handled by fsel.
case ISD::SETULT: case ISD::SETULT:
case ISD::SETLT: case ISD::SETLT:
Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS); Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);