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Add basic addressing mode support and one load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
4543251834
commit
bc83fd9672
@ -54,6 +54,7 @@ namespace {
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}
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void printOperand(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -182,6 +183,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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if (CloseParen) O << ")";
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}
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void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
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printOperand(MI, opNum);
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O << "+";
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printOperand(MI, opNum+1);
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}
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bool SparcV8AsmPrinter::doInitialization(Module &M) {
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Mang = new Mangler(M);
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return false; // success
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@ -187,6 +187,10 @@ public:
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SDOperand Select(SDOperand Op);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
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bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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@ -214,6 +218,22 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand N, SDOperand &R1,
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SDOperand &R2) {
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// FIXME: This should obviously be smarter.
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R1 = Select(N);
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R2 = CurDAG->getRegister(V8::G0, MVT::i32);
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand N, SDOperand &Base,
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SDOperand &Offset) {
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// FIXME: This should obviously be smarter.
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Base = Select(N);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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@ -52,6 +52,22 @@ def SETHIimm : PatLeaf<(imm), [{
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return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
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}], HI22>;
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// Addressing modes.
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def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
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def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
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// Address operands
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def MEMrr : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops IntRegs, IntRegs);
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}
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def MEMri : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops IntRegs, i32imm);
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -104,8 +120,9 @@ def LDUH: F3_2<3, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"lduh [$b+$c], $dst", []>;
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def LD : F3_2<3, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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(ops IntRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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def LDD : F3_2<3, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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@ -586,4 +603,4 @@ def : Pat<(i32 simm13:$val),
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(ORri G0, imm:$val)>;
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// Arbitrary immediates.
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def : Pat<(i32 imm:$val),
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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@ -54,6 +54,7 @@ namespace {
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}
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void printOperand(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum);
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bool printInstruction(const MachineInstr *MI); // autogenerated.
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bool runOnMachineFunction(MachineFunction &F);
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bool doInitialization(Module &M);
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@ -182,6 +183,13 @@ void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
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if (CloseParen) O << ")";
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}
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void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
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printOperand(MI, opNum);
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O << "+";
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printOperand(MI, opNum+1);
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}
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bool SparcV8AsmPrinter::doInitialization(Module &M) {
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Mang = new Mangler(M);
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return false; // success
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@ -187,6 +187,10 @@ public:
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SDOperand Select(SDOperand Op);
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
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bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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@ -214,6 +218,22 @@ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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ScheduleAndEmitDAG(DAG);
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}
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bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand N, SDOperand &R1,
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SDOperand &R2) {
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// FIXME: This should obviously be smarter.
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R1 = Select(N);
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R2 = CurDAG->getRegister(V8::G0, MVT::i32);
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return true;
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}
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bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand N, SDOperand &Base,
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SDOperand &Offset) {
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// FIXME: This should obviously be smarter.
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Base = Select(N);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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@ -52,6 +52,22 @@ def SETHIimm : PatLeaf<(imm), [{
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return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
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}], HI22>;
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// Addressing modes.
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def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
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def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
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// Address operands
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def MEMrr : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops IntRegs, IntRegs);
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}
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def MEMri : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let NumMIOperands = 2;
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let MIOperandInfo = (ops IntRegs, i32imm);
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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@ -104,8 +120,9 @@ def LDUH: F3_2<3, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"lduh [$b+$c], $dst", []>;
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def LD : F3_2<3, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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(ops IntRegs:$dst, MEMri:$addr),
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"ld [$addr], $dst",
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[(set IntRegs:$dst, (load ADDRri:$addr))]>;
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def LDD : F3_2<3, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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@ -586,4 +603,4 @@ def : Pat<(i32 simm13:$val),
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(ORri G0, imm:$val)>;
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// Arbitrary immediates.
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def : Pat<(i32 imm:$val),
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
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