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ARM vpush/vpop assembler mnemonics accept an optional size suffix.
rdar://10988114 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -206,6 +206,14 @@ def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>,
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Requires<[HasVFP2]>;
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def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>,
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Requires<[HasVFP2]>;
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defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
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(VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
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defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
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(VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>;
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defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
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(VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>;
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defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
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(VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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@ -7,6 +7,21 @@ foo:
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vpush {s8, s9, s10, s11, s12}
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vpop {d8, d9, d10, d11, d12}
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vpop {s8, s9, s10, s11, s12}
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@ optional size suffix
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vpush.s8 {d8, d9, d10, d11, d12}
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vpush.16 {s8, s9, s10, s11, s12}
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vpop.f32 {d8, d9, d10, d11, d12}
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vpop.64 {s8, s9, s10, s11, s12}
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@ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
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@ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a]
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@ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b]
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@ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a]
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@ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed]
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@ CHECK-ARM: vpush {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0x2d,0xed]
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@ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec]
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@ CHECK-ARM: vpop {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0xbd,0xec]
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@ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b]
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@ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a]
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