From bdf370d28b60a2144e725ba7ccedc8205077c6d7 Mon Sep 17 00:00:00 2001 From: Eugene Zelenko Date: Wed, 11 Jan 2017 01:45:03 +0000 Subject: [PATCH] [Target] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291641 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetLowering.h | 143 ++++++++++-------- include/llvm/Target/TargetMachine.h | 30 ++-- include/llvm/Target/TargetSubtargetInfo.h | 20 +-- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h | 19 ++- lib/Target/ARM/ARMISelLowering.h | 41 +++-- 5 files changed, 143 insertions(+), 110 deletions(-) diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index a68bd9cdf06..3728a7a8cb1 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -23,66 +23,80 @@ #ifndef LLVM_TARGET_TARGETLOWERING_H #define LLVM_TARGET_TARGETLOWERING_H +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/DAGCombine.h" +#include "llvm/CodeGen/ISDOpcodes.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/RuntimeLibcalls.h" #include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/CodeGen/ValueTypes.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/CallSite.h" #include "llvm/IR/CallingConv.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/InlineAsm.h" +#include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/Type.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/Support/AtomicOrdering.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetCallingConv.h" #include "llvm/Target/TargetMachine.h" +#include +#include #include +#include +#include #include +#include +#include #include namespace llvm { - class BranchProbability; - class CallInst; - class CCState; - class CCValAssign; - class FastISel; - class FunctionLoweringInfo; - class ImmutableCallSite; - class IntrinsicInst; - class MachineBasicBlock; - class MachineFunction; - class MachineInstr; - class MachineJumpTableInfo; - class MachineLoop; - class MachineRegisterInfo; - class Mangler; - class MCContext; - class MCExpr; - class MCSymbol; - template class SmallVectorImpl; - class DataLayout; - class TargetRegisterClass; - class TargetLibraryInfo; - class TargetLoweringObjectFile; - class Value; - namespace Sched { - enum Preference { - None, // No preference - Source, // Follow source order. - RegPressure, // Scheduling for lowest register pressure. - Hybrid, // Scheduling for both latency and register pressure. - ILP, // Scheduling for ILP in low register pressure mode. - VLIW // Scheduling for VLIW targets. - }; - } +class BranchProbability; +class CCState; +class CCValAssign; +class FastISel; +class FunctionLoweringInfo; +class IntrinsicInst; +class MachineBasicBlock; +class MachineFunction; +class MachineInstr; +class MachineJumpTableInfo; +class MachineLoop; +class MachineRegisterInfo; +class MCContext; +class MCExpr; +class TargetRegisterClass; +class TargetLibraryInfo; +class TargetRegisterInfo; +class Value; + +namespace Sched { + + enum Preference { + None, // No preference + Source, // Follow source order. + RegPressure, // Scheduling for lowest register pressure. + Hybrid, // Scheduling for both latency and register pressure. + ILP, // Scheduling for ILP in low register pressure mode. + VLIW // Scheduling for VLIW targets. + }; + +} // end namespace Sched /// This base class for TargetLowering contains the SelectionDAG-independent /// parts that can be used from the rest of CodeGen. class TargetLoweringBase { - TargetLoweringBase(const TargetLoweringBase&) = delete; - void operator=(const TargetLoweringBase&) = delete; - public: /// This enum indicates whether operations are valid for a target, and if not, /// what action should be used to make them valid. @@ -166,7 +180,9 @@ public: /// NOTE: The TargetMachine owns TLOF. explicit TargetLoweringBase(const TargetMachine &TM); - virtual ~TargetLoweringBase() {} + TargetLoweringBase(const TargetLoweringBase&) = delete; + void operator=(const TargetLoweringBase&) = delete; + virtual ~TargetLoweringBase() = default; protected: /// \brief Initialize all of the actions to default values. @@ -599,19 +615,18 @@ public: MVT &RegisterVT) const; struct IntrinsicInfo { - unsigned opc; // target opcode - EVT memVT; // memory VT - const Value* ptrVal; // value representing memory location - int offset; // offset off of ptrVal - unsigned size; // the size of the memory location - // (taken from memVT if zero) - unsigned align; // alignment - bool vol; // is volatile? - bool readMem; // reads memory? - bool writeMem; // writes memory? + unsigned opc = 0; // target opcode + EVT memVT; // memory VT + const Value* ptrVal = nullptr; // value representing memory location + int offset = 0; // offset off of ptrVal + unsigned size = 0; // the size of the memory location + // (taken from memVT if zero) + unsigned align = 1; // alignment + bool vol = false; // is volatile? + bool readMem = false; // reads memory? + bool writeMem = false; // writes memory? - IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1), - vol(false), readMem(false), writeMem(false) {} + IntrinsicInfo() = default; }; /// Given an intrinsic, checks if on the target the intrinsic will need to map @@ -823,7 +838,6 @@ public: getCondCodeAction(CC, VT) == Custom; } - /// If the action for this operation is to promote, this method returns the /// ValueType to promote to. MVT getTypeToPromoteTo(unsigned Op, MVT VT) const { @@ -1643,11 +1657,11 @@ public: /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with /// no scale. struct AddrMode { - GlobalValue *BaseGV; - int64_t BaseOffs; - bool HasBaseReg; - int64_t Scale; - AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {} + GlobalValue *BaseGV = nullptr; + int64_t BaseOffs = 0; + bool HasBaseReg = false; + int64_t Scale = 0; + AddrMode() = default; }; /// Return true if the addressing mode represented by AM is legal for this @@ -2093,8 +2107,6 @@ protected: private: LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const; -private: - /// Targets can specify ISD nodes that they would like PerformDAGCombine /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this /// array. @@ -2192,7 +2204,6 @@ protected: /// \see enableExtLdPromotion. bool EnableExtLdPromotion; -protected: /// Return true if the value types that can be represented by the specified /// register class are all legal. bool isLegalRC(const TargetRegisterClass *RC) const; @@ -2209,12 +2220,12 @@ protected: /// This class also defines callbacks that targets must implement to lower /// target-specific constructs to SelectionDAG operators. class TargetLowering : public TargetLoweringBase { - TargetLowering(const TargetLowering&) = delete; - void operator=(const TargetLowering&) = delete; - public: struct DAGCombinerInfo; + TargetLowering(const TargetLowering&) = delete; + void operator=(const TargetLowering&) = delete; + /// NOTE: The TargetMachine owns TLOF. explicit TargetLowering(const TargetMachine &TM); @@ -2376,6 +2387,7 @@ public: void *DC; // The DAG Combiner object. CombineLevel Level; bool CalledByLegalizer; + public: SelectionDAG &DAG; @@ -2542,7 +2554,7 @@ public: ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), isSRet(false), isNest(false), isByVal(false), isInAlloca(false), isReturned(false), isSwiftSelf(false), isSwiftError(false), - Alignment(0) { } + Alignment(0) {} void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx); }; @@ -2681,7 +2693,6 @@ public: ArgListTy &getArgs() { return Args; } - }; /// This function lowers an abstract call to a function into an actual call. @@ -3176,6 +3187,6 @@ void GetReturnInfo(Type *ReturnType, AttributeSet attr, SmallVectorImpl &Outs, const TargetLowering &TLI, const DataLayout &DL); -} // end llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_TARGET_TARGETLOWERING_H diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 8991b9baede..b1d8f8f1e91 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -20,36 +20,26 @@ #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetOptions.h" -#include #include namespace llvm { -class InstrItineraryData; class GlobalValue; -class Mangler; class MachineFunctionInitializer; -class MachineModuleInfo; +class Mangler; class MCAsmInfo; class MCContext; class MCInstrInfo; class MCRegisterInfo; class MCSubtargetInfo; class MCSymbol; -class Target; -class TargetLibraryInfo; -class TargetFrameLowering; -class TargetIRAnalysis; -class TargetIntrinsicInfo; -class TargetLowering; -class TargetPassConfig; -class TargetRegisterInfo; -class TargetSubtargetInfo; -class TargetTransformInfo; -class formatted_raw_ostream; -class raw_ostream; class raw_pwrite_stream; +class Target; +class TargetIntrinsicInfo; +class TargetIRAnalysis; class TargetLoweringObjectFile; +class TargetPassConfig; +class TargetSubtargetInfo; // The old pass manager infrastructure is hidden in a legacy namespace now. namespace legacy { @@ -64,8 +54,6 @@ using legacy::PassManagerBase; /// interface. /// class TargetMachine { - TargetMachine(const TargetMachine &) = delete; - void operator=(const TargetMachine &) = delete; protected: // Can only create subclasses. TargetMachine(const Target &T, StringRef DataLayoutString, const Triple &TargetTriple, StringRef CPU, StringRef FS, @@ -106,6 +94,8 @@ public: const TargetOptions DefaultOptions; mutable TargetOptions Options; + TargetMachine(const TargetMachine &) = delete; + void operator=(const TargetMachine &) = delete; virtual ~TargetMachine(); const Target &getTarget() const { return TheTarget; } @@ -311,6 +301,6 @@ public: bool DisableVerify = true) override; }; -} // End llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_TARGET_TARGETMACHINE_H diff --git a/include/llvm/Target/TargetSubtargetInfo.h b/include/llvm/Target/TargetSubtargetInfo.h index bf4331383cb..0b435159602 100644 --- a/include/llvm/Target/TargetSubtargetInfo.h +++ b/include/llvm/Target/TargetSubtargetInfo.h @@ -14,23 +14,26 @@ #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H #define LLVM_TARGET_TARGETSUBTARGETINFO_H +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/PBQPRAConstraint.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/ScheduleDAGMutation.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/CodeGen.h" +#include #include namespace llvm { class CallLowering; -class DataLayout; class InstructionSelector; class LegalizerInfo; -class MachineFunction; class MachineInstr; class RegisterBankInfo; class SDep; +class SelectionDAGTargetInfo; class SUnit; class TargetFrameLowering; class TargetInstrInfo; @@ -38,9 +41,7 @@ class TargetLowering; class TargetRegisterClass; class TargetRegisterInfo; class TargetSchedModel; -class SelectionDAGTargetInfo; struct MachineSchedPolicy; -template class SmallVectorImpl; //===----------------------------------------------------------------------===// /// @@ -49,10 +50,6 @@ template class SmallVectorImpl; /// be exposed through a TargetSubtargetInfo-derived class. /// class TargetSubtargetInfo : public MCSubtargetInfo { - TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; - void operator=(const TargetSubtargetInfo &) = delete; - TargetSubtargetInfo() = delete; - protected: // Can only create subclasses... TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS, ArrayRef PF, @@ -69,6 +66,9 @@ public: typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; typedef SmallVectorImpl RegClassVector; + TargetSubtargetInfo() = delete; + TargetSubtargetInfo(const TargetSubtargetInfo &) = delete; + void operator=(const TargetSubtargetInfo &) = delete; virtual ~TargetSubtargetInfo(); virtual bool isXRaySupported() const { return false; } @@ -229,6 +229,6 @@ public: virtual bool enableSubRegLiveness() const { return false; } }; -} // End llvm namespace +} // end namespace llvm -#endif +#endif // LLVM_TARGET_TARGETSUBTARGETINFO_H diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h index 5cc806668b1..a058942c568 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h @@ -15,10 +15,20 @@ #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H #define LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H +#include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/Support/Casting.h" +#include +#include +#include namespace llvm { + +class InstrItineraryData; + /// ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs. /// /// Edges between SUnits are initially based on edges in the SelectionDAG, @@ -44,7 +54,7 @@ namespace llvm { explicit ScheduleDAGSDNodes(MachineFunction &mf); - ~ScheduleDAGSDNodes() override {} + ~ScheduleDAGSDNodes() override = default; /// Run - perform scheduling. /// @@ -131,6 +141,7 @@ namespace llvm { unsigned DefIdx; unsigned NodeNumDefs; MVT ValueType; + public: RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD); @@ -150,6 +161,7 @@ namespace llvm { } void Advance(); + private: void InitNodeNumDefs(); }; @@ -175,6 +187,7 @@ namespace llvm { void EmitPhysRegCopy(SUnit *SU, DenseMap &VRBaseMap, MachineBasicBlock::iterator InsertPos); }; -} -#endif +} // end namespace llvm + +#endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SCHEDULEDAGSDNODES_H diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 5255d82d647..7a7f91f4d3c 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -16,16 +16,28 @@ #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H #include "MCTargetDesc/ARMBaseInfo.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" +#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/InlineAsm.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Target/TargetLowering.h" -#include +#include namespace llvm { - class ARMConstantPoolValue; - class ARMSubtarget; + +class ARMSubtarget; +class InstrItineraryData; namespace ARMISD { + // ARM Specific DAG Nodes enum NodeType : unsigned { // Start the numbering where the builtin ops and target ops leave off. @@ -217,12 +229,15 @@ namespace llvm { VST3LN_UPD, VST4LN_UPD }; - } + + } // end namespace ARMISD /// Define some predicates that are used for node matching. namespace ARM { + bool isBitFieldInvertedMask(unsigned v); - } + + } // end namespace ARM //===--------------------------------------------------------------------===// // ARMTargetLowering - ARM Implementation of the TargetLowering interface @@ -531,6 +546,7 @@ namespace llvm { std::pair getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; typedef SmallVector, 8> RegsToPassVector; + void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, @@ -623,6 +639,7 @@ namespace llvm { return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && MF->getFunction()->hasFnAttribute(Attribute::NoUnwind); } + void initializeSplitCSR(MachineBasicBlock *Entry) const override; void insertCopiesSplitCSR( MachineBasicBlock *Entry, @@ -644,9 +661,8 @@ namespace llvm { unsigned ArgOffset, unsigned TotalArgRegsSaveSize, bool ForceMutable = false) const; - SDValue - LowerCall(TargetLowering::CallLoweringInfo &CLI, - SmallVectorImpl &InVals) const override; + SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, + SmallVectorImpl &InVals) const override; /// HandleByVal - Target-specific cleanup for ByVal support. void HandleByVal(CCState *, unsigned &, unsigned) const override; @@ -712,9 +728,12 @@ namespace llvm { }; namespace ARM { + FastISel *createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo); - } -} -#endif // ARMISELLOWERING_H + } // end namespace ARM + +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H