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Add an MF argument to MI::copyImplicitOps().

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This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.

Also add a corresponding MachineInstrBuilder method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-12-20 22:54:02 +00:00
parent 9500e5d07a
commit be06aacaa9
7 changed files with 15 additions and 8 deletions
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2
include/llvm/CodeGen/MachineInstr.h
View File

@ -929,7 +929,7 @@ public:
/// copyImplicitOps - Copy implicit register operands from specified
/// instruction to this instruction.
void copyImplicitOps(const MachineInstr *MI);
void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
//
// Debugging support

6
include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -208,6 +208,12 @@ public:
}
}
}
/// Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder &copyImplicitOps(const MachineInstr *OtherMI) {
MI->copyImplicitOps(*MF, OtherMI);
return *this;
}
};
/// BuildMI - Builder interface. Specify how to create the initial instruction

5
lib/CodeGen/MachineInstr.cpp
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@ -1403,12 +1403,13 @@ bool MachineInstr::allDefsAreDead() const {
/// copyImplicitOps - Copy implicit register operands from specified
/// instruction to this instruction.
void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
void MachineInstr::copyImplicitOps(MachineFunction &MF,
const MachineInstr *MI) {
for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isImplicit())
addOperand(MO);
addOperand(MF, MO);
}
}

2
lib/Target/ARM/ARMFrameLowering.cpp
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@ -696,7 +696,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
for (unsigned i = 0, e = Regs.size(); i < e; ++i)
MIB.addReg(Regs[i], getDefRegState(true));
if (DeleteRet) {
MIB->copyImplicitOps(&*MI);
MIB.copyImplicitOps(&*MI);
MI->eraseFromParent();
}
MI = MIB;

2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -1408,7 +1408,7 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
Opcode == ARM::LDMIA_UPD) && "Unsupported multiple load-return!");
PrevMI->setDesc(TII->get(NewOpc));
MO.setReg(ARM::PC);
PrevMI->copyImplicitOps(&*MBBI);
PrevMI->copyImplicitOps(*MBB.getParent(), &*MBBI);
MBB.erase(MBBI);
return true;
}

4
lib/Target/ARM/Thumb1FrameLowering.cpp
View File

@ -281,7 +281,7 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
.addReg(ARM::R3, RegState::Kill);
AddDefaultPred(MIB);
MIB->copyImplicitOps(&*MBBI);
MIB.copyImplicitOps(&*MBBI);
// erase the old tBX_RET instruction
MBB.erase(MBBI);
}
@ -352,7 +352,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
continue;
Reg = ARM::PC;
(*MIB).setDesc(TII.get(ARM::tPOP_RET));
MIB->copyImplicitOps(&*MI);
MIB.copyImplicitOps(&*MI);
MI = MBB.erase(MI);
}
MIB.addReg(Reg, getDefRegState(true));

2
lib/Target/X86/X86FrameLowering.cpp
View File

@ -1138,7 +1138,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF,
}
MachineInstr *NewMI = prior(MBBI);
NewMI->copyImplicitOps(MBBI);
NewMI->copyImplicitOps(MF, MBBI);
// Delete the pseudo instruction TCRETURN.
MBB.erase(MBBI);