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really kill off the last MRMInitReg inst, remove logic from encoder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95437 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -384,6 +384,7 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
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case X86::MMX_V_SETALLONES:
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LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
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case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
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case X86::V_SET0: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
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case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
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@ -1610,8 +1610,7 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
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// when we have a better way to specify isel priority.
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let Defs = [EFLAGS],
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AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins),
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"",
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def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "",
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[(set GR64:$dst, 0)]>;
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// Materialize i64 constant where top 32-bits are zero. This could theoretically
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@ -506,9 +506,9 @@ def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
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canFoldAsLoad = 1 in
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// FIXME: Set encoding to pseudo!
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def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
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"", [(set FR32:$dst, fp32imm0)]>,
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Requires<[HasSSE1]>, TB, OpSize;
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def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
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[(set FR32:$dst, fp32imm0)]>,
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Requires<[HasSSE1]>, TB, OpSize;
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// Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
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// disregarded.
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@ -1270,8 +1270,8 @@ def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
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// Alias instructions that map fld0 to pxor for sse.
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
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canFoldAsLoad = 1 in
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def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
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"pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
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def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
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[(set FR64:$dst, fpimm0)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
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@ -364,10 +364,10 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
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--NumOps;
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// FIXME: Can we kill off MRMInitReg??
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unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
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switch (TSFlags & X86II::FormMask) {
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case X86II::MRMInitReg:
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assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
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default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
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assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
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case X86II::RawFrm: {
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@ -547,14 +547,6 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
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#endif
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break;
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}
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case X86II::MRMInitReg:
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EmitByte(BaseOpcode, OS);
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// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
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EmitRegModRMByte(MI.getOperand(CurOp),
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GetX86RegNum(MI.getOperand(CurOp)), OS);
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++CurOp;
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break;
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}
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#ifndef NDEBUG
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