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Remove getAllocatedRegNum(). Use getReg() instead.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-02-13 21:01:20 +00:00
parent 903b22cd51
commit be766c7246
20 changed files with 49 additions and 54 deletions
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5
include/llvm/CodeGen/MachineInstr.h
View File

@ -277,15 +277,12 @@ public:
}
// used to get the reg number if when one is allocated
int getAllocatedRegNum() const {
unsigned getReg() const {
assert(hasAllocatedReg());
return regNum;
}
// ********** TODO: get rid of this duplicate code! ***********
unsigned getReg() const {
return getAllocatedRegNum();
}
void setReg(unsigned Reg) {
assert(hasAllocatedReg() && "This operand cannot have a register number!");
regNum = Reg;

2
include/llvm/Target/TargetRegInfo.h
View File

@ -149,7 +149,7 @@ public:
// returns the register that is hardwired to zero if any (-1 if none)
//
virtual int getZeroRegNum() const = 0;
virtual unsigned getZeroRegNum() const = 0;
// Number of registers used for passing int args (usually 6: %o0 - %o5)
// and float args (usually 32: %f0 - %f31)

8
lib/CodeGen/InstrSched/SchedGraph.cpp
View File

@ -487,11 +487,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.hasAllocatedReg()) {
int regNum = mop.getAllocatedRegNum();
unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
if (regNum != target.getRegInfo().getZeroRegNum())
regToRefVecMap[mop.getAllocatedRegNum()]
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
// If this is a volatile register, add the instruction to callDepVec
@ -528,9 +528,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
int regNum = mop.getAllocatedRegNum();
unsigned regNum = mop.getReg();
if (regNum != target.getRegInfo().getZeroRegNum())
regToRefVecMap[mop.getAllocatedRegNum()]
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
}

4
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -115,7 +115,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
const MachineOperand& mop = mi->getOperand(i);
if (mop.isRegister() &&
MRegisterInfo::isVirtualRegister(mop.getReg())) {
unsigned reg = mop.getAllocatedRegNum();
unsigned reg = mop.getReg();
Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
assert(r2iit != r2iMap_.end());
r2iit->second->weight += pow(10.0F, loopDepth);
@ -313,7 +313,7 @@ void LiveIntervals::computeIntervals()
MachineOperand& mop = mi->getOperand(i);
// handle register defs - build intervals
if (mop.isRegister() && mop.isDef())
handleRegisterDef(mbb, mi, mop.getAllocatedRegNum());
handleRegisterDef(mbb, mi, mop.getReg());
}
}
}

10
lib/CodeGen/MachineInstr.cpp
View File

@ -187,7 +187,7 @@ static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
static inline void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) {
if (MRI) {
if (RegNo < MRegisterInfo::FirstVirtualRegister)
if (MRegisterInfo::isPhysicalRegister(RegNo))
os << "%" << MRI->get(RegNo).Name;
else
os << "%reg" << RegNo;
@ -219,14 +219,14 @@ static void print(const MachineOperand &MO, std::ostream &OS,
OS << "==";
}
if (MO.hasAllocatedReg())
OutputReg(OS, MO.getAllocatedRegNum(), MRI);
OutputReg(OS, MO.getReg(), MRI);
break;
case MachineOperand::MO_CCRegister:
OS << "%ccreg";
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
OutputReg(OS, MO.getAllocatedRegNum(), MRI);
OutputReg(OS, MO.getReg(), MRI);
}
break;
case MachineOperand::MO_MachineRegister:
@ -360,7 +360,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
{
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
OutputReg(OS, MO.getAllocatedRegNum());
OutputReg(OS, MO.getReg());
if (MO.getVRegValue()) {
if (MO.hasAllocatedReg()) OS << "==";
@ -373,7 +373,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
OutputValue(OS, MO.getVRegValue());
if (MO.hasAllocatedReg()) {
OS << "==";
OutputReg(OS, MO.getAllocatedRegNum());
OutputReg(OS, MO.getReg());
}
break;
case MachineOperand::MO_MachineRegister:

2
lib/CodeGen/PHIElimination.cpp
View File

@ -76,7 +76,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
assert(MRegisterInfo::isVirtualRegister(MI->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
unsigned DestReg = MI->getOperand(0).getAllocatedRegNum();
unsigned DestReg = MI->getOperand(0).getReg();
// Create a new register for the incoming PHI arguments
const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);

2
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -443,7 +443,7 @@ bool RA::runOnMachineFunction(MachineFunction &fn) {
MachineOperand& op = currentInstr_->getOperand(i);
if (op.isRegister() && op.isUse() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtReg = op.getAllocatedRegNum();
unsigned virtReg = op.getReg();
unsigned physReg = 0;
Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
if (it != v2pMap_.end()) {

6
lib/CodeGen/RegAllocLocal.cpp
View File

@ -517,7 +517,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
if (MI->getOperand(i).isUse() &&
!MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
unsigned VirtSrcReg = MI->getOperand(i).getReg();
unsigned PhysSrcReg = reloadVirtReg(MBB, MI, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
}
@ -551,7 +551,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isPhysicalRegister(MI->getOperand(i).getReg())) {
unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
unsigned Reg = MI->getOperand(i).getReg();
spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg
PhysRegsUsed[Reg] = 0; // It is free and reserved now
PhysRegsUseOrder.push_back(Reg);
@ -584,7 +584,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isDef() && MI->getOperand(i).isRegister() &&
MRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg())) {
unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
unsigned DestVirtReg = MI->getOperand(i).getReg();
unsigned DestPhysReg;
// If DestVirtReg already has a value, use it.

8
lib/CodeGen/RegAllocSimple.cpp
View File

@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
MachineOperand &op = MI->getOperand(i);
if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, *TM));
@ -187,11 +187,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
MI->getOperand(1).getAllocatedRegNum() &&
MI->getOperand(1).getReg() &&
MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
physReg = MI->getOperand(1).getAllocatedRegNum();
physReg = MI->getOperand(1).getReg();
} else {
physReg = getFreeReg(virtualReg);
}
@ -205,7 +205,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
MI->SetMachineOperandReg(i, physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getAllocatedRegNum() << "\n");
", phys: " << op.getReg() << "\n");
}
}
RegClassIdx.clear();

12
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -97,14 +97,14 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
assert(mi->getOperand(1).isRegister() &&
mi->getOperand(1).getAllocatedRegNum() &&
mi->getOperand(1).getReg() &&
mi->getOperand(1).isUse() &&
"two address instruction invalid");
// if the two operands are the same we just remove the use
// and mark the def as def&use
if (mi->getOperand(0).getAllocatedRegNum() ==
mi->getOperand(1).getAllocatedRegNum()) {
if (mi->getOperand(0).getReg() ==
mi->getOperand(1).getReg()) {
}
else {
MadeChange = true;
@ -114,8 +114,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
// to:
// a = b
// a = a op c
unsigned regA = mi->getOperand(0).getAllocatedRegNum();
unsigned regB = mi->getOperand(1).getAllocatedRegNum();
unsigned regA = mi->getOperand(0).getReg();
unsigned regB = mi->getOperand(1).getReg();
assert(MRegisterInfo::isVirtualRegister(regA) &&
MRegisterInfo::isVirtualRegister(regB) &&
@ -127,7 +127,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
// because we are in SSA form.
for (unsigned i = 1; i != mi->getNumOperands(); ++i)
assert(!mi->getOperand(i).isRegister() ||
mi->getOperand(i).getAllocatedRegNum() != (int)regA);
mi->getOperand(i).getReg() != regA);
const TargetRegisterClass* rc =
MF.getSSARegMap()->getRegClass(regA);

8
lib/Target/SparcV9/InstrSched/SchedGraph.cpp
View File

@ -487,11 +487,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.hasAllocatedReg()) {
int regNum = mop.getAllocatedRegNum();
unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
if (regNum != target.getRegInfo().getZeroRegNum())
regToRefVecMap[mop.getAllocatedRegNum()]
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
// If this is a volatile register, add the instruction to callDepVec
@ -528,9 +528,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
int regNum = mop.getAllocatedRegNum();
unsigned regNum = mop.getReg();
if (regNum != target.getRegInfo().getZeroRegNum())
regToRefVecMap[mop.getAllocatedRegNum()]
regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
}

3
lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
View File

@ -71,7 +71,8 @@ ChooseRegOrImmed(int64_t intValue,
opType = isSigned? MachineOperand::MO_SignExtendedImmed
: MachineOperand::MO_UnextendedImmed;
getImmedValue = intValue;
} else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0) {
} else if (intValue == 0 &&
target.getRegInfo().getZeroRegNum() != (unsigned)-1) {
opType = MachineOperand::MO_MachineRegister;
getMachineRegNum = target.getRegInfo().getZeroRegNum();
}

7
lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
View File

@ -194,9 +194,8 @@ void LiveRangeInfo::constructLiveRanges() {
// set it directly in the LiveRange
if (OpI.getMachineOperand().hasAllocatedReg()) {
unsigned getClassId;
LR->setColor(MRI.getClassRegNum(
OpI.getMachineOperand().getAllocatedRegNum(),
getClassId));
LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
getClassId));
}
}
@ -212,7 +211,7 @@ void LiveRangeInfo::constructLiveRanges() {
if (MInst->getImplicitOp(i).hasAllocatedReg()) {
unsigned getClassId;
LR->setColor(MRI.getClassRegNum(
MInst->getImplicitOp(i).getAllocatedRegNum(),
MInst->getImplicitOp(i).getReg(),
getClassId));
}
}

5
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -1019,12 +1019,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
// explicit and implicit operands are set.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).hasAllocatedReg())
markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
if (MI->getImplicitOp(i).hasAllocatedReg())
markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
RegType,MRI);
markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
// Add all of the scratch registers that are used to save values across the
// instruction (e.g., for saving state register values).

2
lib/Target/SparcV9/SparcV9AsmPrinter.cpp
View File

@ -637,7 +637,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
case MachineOperand::MO_CCRegister:
case MachineOperand::MO_MachineRegister:
{
int regNum = (int)mop.getAllocatedRegNum();
int regNum = (int)mop.getReg();
if (regNum == Target.getRegInfo().getInvalidRegNum()) {
// better to print code with NULL registers than to die

2
lib/Target/SparcV9/SparcV9CodeEmitter.cpp
View File

@ -661,7 +661,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
// This is necessary because the Sparc backend doesn't actually lay out
// registers in the real fashion -- it skips those that it chooses not to
// allocate, i.e. those that are the FP, SP, etc.
unsigned fakeReg = MO.getAllocatedRegNum();
unsigned fakeReg = MO.getReg();
unsigned realRegByClass = getRealRegNum(fakeReg, MI);
DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
<< realRegByClass << " (LLC: "

9
lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
View File

@ -63,16 +63,15 @@ DeleteInstruction(MachineBasicBlock& mvec,
static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
return (// both operands are allocated to the same register
MI->getOperand(0).getAllocatedRegNum() ==
MI->getOperand(1).getAllocatedRegNum());
MI->getOperand(0).getReg() == MI->getOperand(1).getReg());
} else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
unsigned srcWithDestReg;
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
MI->getOperand(srcWithDestReg).getAllocatedRegNum()
== MI->getOperand(2).getAllocatedRegNum())
MI->getOperand(srcWithDestReg).getReg()
== MI->getOperand(2).getReg())
break;
if (srcWithDestReg == 2)
@ -82,7 +81,7 @@ static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
unsigned otherOp = 1 - srcWithDestReg;
return (// either operand otherOp is register %g0
(MI->getOperand(otherOp).hasAllocatedReg() &&
MI->getOperand(otherOp).getAllocatedRegNum() ==
MI->getOperand(otherOp).getReg() ==
target.getRegInfo().getZeroRegNum()) ||
// or operand otherOp == 0

2
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@ -52,7 +52,7 @@ SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
// getZeroRegNum - returns the register that contains always zero.
// this is the unified register number
//
int SparcRegInfo::getZeroRegNum() const {
unsigned SparcRegInfo::getZeroRegNum() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::g0);
}

2
lib/Target/SparcV9/SparcV9RegInfo.h
View File

@ -86,7 +86,7 @@ public:
// getZeroRegNum - returns the register that contains always zero this is the
// unified register number
//
virtual int getZeroRegNum() const;
virtual unsigned getZeroRegNum() const;
// getCallAddressReg - returns the reg used for pushing the address when a
// function is called. This can be used for other purposes between calls

4
lib/Target/X86/X86InstrInfo.cpp
View File

@ -61,8 +61,8 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"invalid register-register move instruction");
sourceReg = MI.getOperand(1).getAllocatedRegNum();
destReg = MI.getOperand(0).getAllocatedRegNum();
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
return false;