Extract method for detecting constant unallocatable physregs.

It is safe to move uses of such registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148259 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2012-01-16 22:34:08 +00:00
parent 61425c0a7f
commit c035c940a6
5 changed files with 30 additions and 42 deletions

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@ -64,6 +64,9 @@ class MachineRegisterInfo {
/// started.
BitVector ReservedRegs;
/// AllocatableRegs - From TRI->getAllocatableSet.
mutable BitVector AllocatableRegs;
/// LiveIns/LiveOuts - Keep track of the physical registers that are
/// livein/liveout of the function. Live in values are typically arguments in
/// registers, live out values are typically return values in registers.
@ -215,7 +218,12 @@ public:
#ifndef NDEBUG
void dumpUses(unsigned RegNo) const;
#endif
/// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
/// throughout the function. It is safe to move instructions that read such
/// a physreg.
bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
//===--------------------------------------------------------------------===//
// Virtual Register Info
//===--------------------------------------------------------------------===//

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@ -81,8 +81,6 @@ namespace {
MachineLoop *CurLoop; // The current loop we are working on.
MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
BitVector AllocatableSet;
// Track 'estimated' register pressure.
SmallSet<unsigned, 32> RegSeen;
SmallVector<unsigned, 8> RegPressure;
@ -331,7 +329,6 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
MFI = MF.getFrameInfo();
MRI = &MF.getRegInfo();
InstrItins = TM->getInstrItineraryData();
AllocatableSet = TRI->getAllocatableSet(MF);
if (PreRegAlloc) {
// Estimate register pressure during pre-regalloc pass.
@ -905,18 +902,8 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
// it could get allocated to something with a def during allocation.
if (!MRI->def_empty(Reg))
if (!MRI->isConstantPhysReg(Reg, *I.getParent()->getParent()))
return false;
if (AllocatableSet.test(Reg))
return false;
// Check for a def among the register's aliases too.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
if (!MRI->def_empty(AliasReg))
return false;
if (AllocatableSet.test(AliasReg))
return false;
}
// Otherwise it's safe to move.
continue;
} else if (!MO.isDead()) {

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@ -263,3 +263,21 @@ void MachineRegisterInfo::dumpUses(unsigned Reg) const {
void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
ReservedRegs = TRI->getReservedRegs(MF);
}
bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
const MachineFunction &MF) const {
assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
// Check if any overlapping register is modified.
for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R)
if (!def_empty(*R))
return false;
// Check if any overlapping register is allocatable so it may be used later.
if (AllocatableRegs.empty())
AllocatableRegs = TRI->getAllocatableSet(MF);
for (const unsigned *R = TRI->getOverlaps(PhysReg); *R; ++R)
if (AllocatableRegs.test(*R))
return false;
return true;
}

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@ -485,21 +485,8 @@ MachineBasicBlock *MachineSinking::FindSuccToSinkTo(MachineInstr *MI,
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
// it could get allocated to something with a def during allocation.
if (!MRI->def_empty(Reg))
if (!MRI->isConstantPhysReg(Reg, *MBB->getParent()))
return NULL;
if (AllocatableSet.test(Reg))
return NULL;
// Check for a def among the register's aliases too.
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
if (!MRI->def_empty(AliasReg))
return NULL;
if (AllocatableSet.test(AliasReg))
return NULL;
}
} else if (!MO.isDead()) {
// A def that isn't dead. We can't move it.
return NULL;

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@ -380,7 +380,6 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
const MachineRegisterInfo &MRI = MF.getRegInfo();
const TargetMachine &TM = MF.getTarget();
const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
// Remat clients assume operand 0 is the defined register.
if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
@ -432,19 +431,8 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
// If the physreg has no defs anywhere, it's just an ambient register
// and we can freely move its uses. Alternatively, if it's allocatable,
// it could get allocated to something with a def during allocation.
if (!MRI.def_empty(Reg))
if (!MRI.isConstantPhysReg(Reg, MF))
return false;
BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
if (AllocatableRegs.test(Reg))
return false;
// Check for a def among the register's aliases too.
for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
unsigned AliasReg = *Alias;
if (!MRI.def_empty(AliasReg))
return false;
if (AllocatableRegs.test(AliasReg))
return false;
}
} else {
// A physreg def. We can't remat it.
return false;