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Revert r296708; causing test failures on ARM hosts.

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Original commit message:

[ARM] Fix insert point for store rescheduling.
    
In ARMPreAllocLoadStoreOpt::RescheduleOps, LastOp should be the last
operation which we want to merge. If we break out of the loop because
an operation has the wrong offset, we shouldn't use that operation as
LastOp.
    
This patch fixes some cases where we would sink stores for no reason.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296718 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2017-03-02 00:08:50 +00:00
parent f3b992a333
commit c0998936de
2 changed files with 30 additions and 42 deletions
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40
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -2161,30 +2161,7 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
unsigned LastBytes = 0;
unsigned NumMove = 0;
for (int i = Ops.size() - 1; i >= 0; --i) {
// Make sure each operation has the same kind.
MachineInstr *Op = Ops[i];
unsigned LSMOpcode
= getLoadStoreMultipleOpcode(Op->getOpcode(), ARM_AM::ia);
if (LastOpcode && LSMOpcode != LastOpcode)
break;
// Check that we have a continuous set of offsets.
int Offset = getMemoryOpOffset(*Op);
unsigned Bytes = getLSMultipleTransferSize(Op);
if (LastBytes) {
if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
break;
}
// Don't try to reschedule too many instructions.
if (++NumMove == 8) // FIXME: Tune this limit.
break;
// Found a mergable instruction; save information about it.
LastOffset = Offset;
LastBytes = Bytes;
LastOpcode = LSMOpcode;
unsigned Loc = MI2LocMap[Op];
if (Loc <= FirstLoc) {
FirstLoc = Loc;
@ -2194,6 +2171,23 @@ bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
LastLoc = Loc;
LastOp = Op;
}
unsigned LSMOpcode
= getLoadStoreMultipleOpcode(Op->getOpcode(), ARM_AM::ia);
if (LastOpcode && LSMOpcode != LastOpcode)
break;
int Offset = getMemoryOpOffset(*Op);
unsigned Bytes = getLSMultipleTransferSize(Op);
if (LastBytes) {
if (Bytes != LastBytes || Offset != (LastOffset + (int)Bytes))
break;
}
LastOffset = Offset;
LastBytes = Bytes;
LastOpcode = LSMOpcode;
if (++NumMove == 8) // FIXME: Tune this limit.
break;
}
if (NumMove <= 1)

32
test/CodeGen/ARM/prera-ldst-insertpt.mir
View File

@ -36,14 +36,6 @@ body: |
t2STRi12 %1, %0, 0, 14, _ :: (store 4)
%10 : rgpr = t2LSLri %2, 1, 14, _, _
t2STRi12 killed %10, %0, 4, 14, _ :: (store 4)
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
; CHECK: t2STRi12 %1,
; CHECK-NEXT: t2STRi12 killed %10,
; CHECK-NEXT: t2MOVi
; CHECK-NEXT: t2ADDrs
%11 : rgpr = t2MOVi 55, 14, _, _
%12 : gprnopc = t2ADDrs %11, killed %7, 19, 14, _, _
t2STRi12 killed %12, %0, 16, 14, _ :: (store 4)
@ -51,7 +43,12 @@ body: |
t2STRi12 killed %13, %0, 20, 14, _ :: (store 4)
; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 killed %12,
; FIXME: Make sure we don't extend the live-range of a store
; when we don't need to.
; CHECK: t2STRi12 %1,
; CHECK-NEXT: t2STRi12 killed %10,
; CHECK-NEXT: %13 = t2ADDrs %11
; CHECK-NEXT: t2STRi12 killed %12,
; CHECK-NEXT: t2STRi12 killed %13,
tBX_RET 14, _
@ -76,15 +73,6 @@ body: |
t2STRi12 killed %10, %0, 4, 14, _ :: (store 4)
%3 : rgpr = t2MUL %2, %2, 14, _
t2STRi12 %3, %0, 8, 14, _ :: (store 4)
; Make sure we move the paired stores next to each other, and
; insert them in an appropriate location.
; CHECK: t2STRi12 {{.*}}, 0
; CHECK-NEXT: t2STRi12 {{.*}}, 4
; CHECK-NEXT: t2STRi12 {{.*}}, 8
; CHECK-NEXT: t2MUL
; CHECK-NEXT: t2MOVi32imm
%4 : rgpr = t2MUL %1, %1, 14, _
%5 : rgpr = t2MOVi32imm -858993459
%6 : rgpr, %7 : rgpr = t2UMULL killed %3, %5, 14, _
@ -97,7 +85,13 @@ body: |
t2STRi12 killed %13, %0, 20, 14, _ :: (store 4)
; Make sure we move the paired stores next to each other.
; CHECK: t2STRi12 {{.*}}, 16
; FIXME: Make sure we don't extend the live-range of a store
; when we don't need to.
; CHECK: t2STRi12 {{.*}}, 0
; CHECK-NEXT: t2STRi12 {{.*}}, 4
; CHECK-NEXT: t2STRi12 {{.*}}, 8
; CHECK-NEXT: t2ADDrs
; CHECK-NEXT: t2STRi12 {{.*}}, 16
; CHECK-NEXT: t2STRi12 {{.*}}, 20
tBX_RET 14, _