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Revert "[mips] Restrict the creation of compact branches"

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This reverts commit rL269893.

Incorrect patch applied.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@269897 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis 2016-05-18 09:51:37 +00:00
parent 6a867d0312
commit c0a6ad42eb
4 changed files with 2 additions and 47 deletions
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25
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
View File

@ -106,26 +106,6 @@ static void LowerDins(MCInst& InstIn) {
return;
}
// Fix a bad compact branch encoding for beqc/bnec.
void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const {
// Encoding may be illegal !(rs < rt), but this situation is
// easily fixed.
unsigned RegOp0 = Inst.getOperand(0).getReg();
unsigned RegOp1 = Inst.getOperand(1).getReg();
unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0);
unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1);
assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!");
if (Reg0 < Reg1)
return;
Inst.getOperand(0).setReg(RegOp1);
Inst.getOperand(1).setReg(RegOp0);
}
bool MipsMCCodeEmitter::isMicroMips(const MCSubtargetInfo &STI) const {
return STI.getFeatureBits()[Mips::FeatureMicroMips];
}
@ -180,11 +160,6 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS,
// Double extract instruction is chosen by pos and size operands
case Mips::DINS:
LowerDins(TmpInst);
break;
// Compact branches.
case Mips::BEQC:
case Mips::BNEC:
LowerCompactBranch(TmpInst);
}
unsigned long N = Fixups.size();

2
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
View File

@ -253,8 +253,6 @@ public:
unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
private:
void LowerCompactBranch(MCInst& Inst) const;
}; // class MipsMCCodeEmitter
} // namespace llvm.

2
lib/Target/Mips/Mips32r6InstrFormats.td
View File

@ -360,7 +360,7 @@ class SPECIAL_SDBBP_FM : MipsR6Inst {
}
// This class is ambiguous with other branches:
// BEQC/BNEC require that rs < rt
// BEQC/BNEC require that rs > rt
class CMP_BRANCH_2R_OFF16_FM<OPGROUP funct> : MipsR6Inst {
bits<5> rs;
bits<5> rt;

20
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -282,16 +282,6 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
}
}
// MIPSR6 forbids both operands being the zero register.
if (Subtarget.hasMips32r6() &&
(I->getOperand(0).getType() == MachineOperand::MO_Register &&
(I->getOperand(0).getReg() == Mips::ZERO ||
I->getOperand(0).getReg() == Mips::ZERO_64)) &&
(I->getOperand(1).getType() == MachineOperand::MO_Register &&
(I->getOperand(1).getReg() == Mips::ZERO ||
I->getOperand(1).getReg() == Mips::ZERO_64)))
return 0;
if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) {
switch (Opcode) {
case Mips::B:
@ -309,12 +299,8 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
else
return Mips::BNEC;
case Mips::BGE:
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
return 0;
return Mips::BGEC;
case Mips::BGEU:
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
return 0;
return Mips::BGEUC;
case Mips::BGEZ:
return Mips::BGEZC;
@ -323,12 +309,8 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
case Mips::BLEZ:
return Mips::BLEZC;
case Mips::BLT:
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
return 0;
return Mips::BLTC;
case Mips::BLTU:
if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
return 0;
return Mips::BLTUC;
case Mips::BLTZ:
return Mips::BLTZC;
@ -348,7 +330,7 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
return Mips::JIC64;
case Mips::JALR64Pseudo:
return Mips::JIALC64;
default:
default:
return 0;
}
}