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AArch64InstPrinter: rewrite of printSysAlias
This is a cleanup/rewrite of the printSysAlias function. This was not using the tablegen instruction descriptions, but was "manually" decoding the instructions. This has been replaced with calls to lookup_XYZ_ByEncoding tablegen calls. This revealed several problems. First, instruction IVAU had the wrong encoding. This was cancelled out by the parser that incorrectly matched the wrong encoding. Second, instruction CVAP was missing from the SystemOperands tablegen descriptions, so this has been added. And third, the required target features were not captured in the tablegen descriptions, so support for this has also been added. Differential Revision: https://reviews.llvm.org/D30329 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296343 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sjoerd Meijer
parent
4042b8120e
commit
c0dc1a30a6
@ -18,35 +18,37 @@ include "llvm/TableGen/SearchableTable.td"
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// AT (address translate) instruction options.
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//===----------------------------------------------------------------------===//
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class AT<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
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class AT<string name, bits<3> op1, bits<4> crn, bits<4> crm,
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bits<3> op2> : SearchableTable {
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let SearchableFields = ["Name", "Encoding"];
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let EnumValueField = "Encoding";
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string Name = name;
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bits<16> Encoding;
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let Encoding{15-14} = op0;
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bits<14> Encoding;
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let Encoding{13-11} = op1;
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let Encoding{10-7} = crn;
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let Encoding{6-3} = crm;
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let Encoding{2-0} = op2;
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code Requires = [{ {} }];
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}
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def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
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def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
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def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
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def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
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def : AT<"S1E2W", 0b01, 0b100, 0b0111, 0b1000, 0b001>;
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def : AT<"S1E3W", 0b01, 0b110, 0b0111, 0b1000, 0b001>;
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def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
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def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
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def : AT<"S12E1R", 0b01, 0b100, 0b0111, 0b1000, 0b100>;
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def : AT<"S12E1W", 0b01, 0b100, 0b0111, 0b1000, 0b101>;
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def : AT<"S12E0R", 0b01, 0b100, 0b0111, 0b1000, 0b110>;
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def : AT<"S12E0W", 0b01, 0b100, 0b0111, 0b1000, 0b111>;
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def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
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def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
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def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
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def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
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def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
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def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
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def : AT<"S1E2W", 0b100, 0b0111, 0b1000, 0b001>;
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def : AT<"S1E3W", 0b110, 0b0111, 0b1000, 0b001>;
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def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
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def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;
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def : AT<"S12E1R", 0b100, 0b0111, 0b1000, 0b100>;
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def : AT<"S12E1W", 0b100, 0b0111, 0b1000, 0b101>;
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def : AT<"S12E0R", 0b100, 0b0111, 0b1000, 0b110>;
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def : AT<"S12E0W", 0b100, 0b0111, 0b1000, 0b111>;
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let Requires = [{ {AArch64::HasV8_2aOps} }] in {
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def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
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def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
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}
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//===----------------------------------------------------------------------===//
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// DMB/DSB (data barrier) instruction options.
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@ -77,28 +79,31 @@ def : DB<"sy", 0xf>;
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// DC (data cache maintenance) instruction options.
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//===----------------------------------------------------------------------===//
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class DC<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
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class DC<string name, bits<3> op1, bits<4> crn, bits<4> crm,
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bits<3> op2> : SearchableTable {
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let SearchableFields = ["Name", "Encoding"];
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let EnumValueField = "Encoding";
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string Name = name;
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bits<16> Encoding;
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let Encoding{15-14} = op0;
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bits<14> Encoding;
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let Encoding{13-11} = op1;
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let Encoding{10-7} = crn;
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let Encoding{6-3} = crm;
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let Encoding{2-0} = op2;
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code Requires = [{ {} }];
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}
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def : DC<"ZVA", 0b01, 0b011, 0b0111, 0b0100, 0b001>;
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def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;
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def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
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def : DC<"CVAC", 0b01, 0b011, 0b0111, 0b1010, 0b001>;
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def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>;
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def : DC<"CVAU", 0b01, 0b011, 0b0111, 0b1011, 0b001>;
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def : DC<"CIVAC", 0b01, 0b011, 0b0111, 0b1110, 0b001>;
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def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>;
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def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;
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def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;
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def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
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def : DC<"CVAC", 0b011, 0b0111, 0b1010, 0b001>;
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def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;
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def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>;
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def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>;
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def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;
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let Requires = [{ {AArch64::HasV8_2aOps} }] in
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def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
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//===----------------------------------------------------------------------===//
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// IC (instruction cache maintenance) instruction options.
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@ -120,7 +125,7 @@ class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
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def : IC<"IALLUIS", 0b000, 0b0111, 0b0001, 0b000, 0>;
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def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;
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def : IC<"IVAU", 0b000, 0b0111, 0b0001, 0b000, 1>;
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def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;
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//===----------------------------------------------------------------------===//
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// ISB (instruction-fetch barrier) instruction options.
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@ -213,14 +218,13 @@ def : PSB<"csync", 0x11>;
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// TLBI (translation lookaside buffer invalidate) instruction options.
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//===----------------------------------------------------------------------===//
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class TLBI<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
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class TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
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bits<3> op2, bit needsreg = 1> : SearchableTable {
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let SearchableFields = ["Name", "Encoding"];
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let EnumValueField = "Encoding";
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string Name = name;
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bits<16> Encoding;
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let Encoding{15-14} = op0;
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bits<14> Encoding;
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let Encoding{13-11} = op1;
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let Encoding{10-7} = crn;
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let Encoding{6-3} = crm;
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@ -228,38 +232,38 @@ class TLBI<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
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bit NeedsReg = needsreg;
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}
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def : TLBI<"IPAS2E1IS", 0b01, 0b100, 0b1000, 0b0000, 0b001>;
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def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>;
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def : TLBI<"VMALLE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b000, 0>;
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def : TLBI<"ALLE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b000, 0>;
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def : TLBI<"ALLE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b000, 0>;
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def : TLBI<"VAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b001>;
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def : TLBI<"VAE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b001>;
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def : TLBI<"VAE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b001>;
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def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>;
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def : TLBI<"VAAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b011>;
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def : TLBI<"ALLE1IS", 0b01, 0b100, 0b1000, 0b0011, 0b100, 0>;
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def : TLBI<"VALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b101>;
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def : TLBI<"VALE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b101>;
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def : TLBI<"VALE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b101>;
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def : TLBI<"VMALLS12E1IS", 0b01, 0b100, 0b1000, 0b0011, 0b110, 0>;
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def : TLBI<"VAALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b111>;
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def : TLBI<"IPAS2E1", 0b01, 0b100, 0b1000, 0b0100, 0b001>;
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def : TLBI<"IPAS2LE1", 0b01, 0b100, 0b1000, 0b0100, 0b101>;
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def : TLBI<"VMALLE1", 0b01, 0b000, 0b1000, 0b0111, 0b000, 0>;
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def : TLBI<"ALLE2", 0b01, 0b100, 0b1000, 0b0111, 0b000, 0>;
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def : TLBI<"ALLE3", 0b01, 0b110, 0b1000, 0b0111, 0b000, 0>;
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def : TLBI<"VAE1", 0b01, 0b000, 0b1000, 0b0111, 0b001>;
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def : TLBI<"VAE2", 0b01, 0b100, 0b1000, 0b0111, 0b001>;
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def : TLBI<"VAE3", 0b01, 0b110, 0b1000, 0b0111, 0b001>;
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def : TLBI<"ASIDE1", 0b01, 0b000, 0b1000, 0b0111, 0b010>;
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def : TLBI<"VAAE1", 0b01, 0b000, 0b1000, 0b0111, 0b011>;
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def : TLBI<"ALLE1", 0b01, 0b100, 0b1000, 0b0111, 0b100, 0>;
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def : TLBI<"VALE1", 0b01, 0b000, 0b1000, 0b0111, 0b101>;
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def : TLBI<"VALE2", 0b01, 0b100, 0b1000, 0b0111, 0b101>;
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def : TLBI<"VALE3", 0b01, 0b110, 0b1000, 0b0111, 0b101>;
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def : TLBI<"VMALLS12E1", 0b01, 0b100, 0b1000, 0b0111, 0b110, 0>;
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def : TLBI<"VAALE1", 0b01, 0b000, 0b1000, 0b0111, 0b111>;
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def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
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def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
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def : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
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def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
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def : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
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def : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
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def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
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def : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
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def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
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def : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
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def : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
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def : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
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def : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>;
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def : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>;
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def : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>;
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def : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>;
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def : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
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def : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
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def : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>;
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def : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>;
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def : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>;
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def : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>;
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def : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>;
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def : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>;
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def : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
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def : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>;
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def : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>;
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def : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>;
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def : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>;
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def : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>;
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def : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;
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def : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;
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//===----------------------------------------------------------------------===//
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@ -739,7 +739,6 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
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assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
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#endif
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const char *Asm = nullptr;
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const MCOperand &Op1 = MI->getOperand(0);
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const MCOperand &Cn = MI->getOperand(1);
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const MCOperand &Cm = MI->getOperand(2);
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@ -750,230 +749,74 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
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unsigned CmVal = Cm.getImm();
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unsigned Op2Val = Op2.getImm();
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uint16_t Encoding = Op2Val;
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Encoding |= CmVal << 3;
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Encoding |= CnVal << 7;
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Encoding |= Op1Val << 11;
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bool NeedsReg;
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std::string Ins;
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std::string Name;
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if (CnVal == 7) {
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switch (CmVal) {
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default:
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break;
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default: return false;
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// IC aliases
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case 1:
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if (Op1Val == 0 && Op2Val == 0)
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Asm = "ic\tialluis";
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break;
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case 5:
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if (Op1Val == 0 && Op2Val == 0)
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Asm = "ic\tiallu";
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else if (Op1Val == 3 && Op2Val == 1)
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Asm = "ic\tivau";
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break;
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case 1: case 5: {
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const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
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if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
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return false;
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NeedsReg = IC->NeedsReg;
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Ins = "ic\t";
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Name = std::string(IC->Name);
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}
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break;
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// DC aliases
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case 4:
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if (Op1Val == 3 && Op2Val == 1)
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Asm = "dc\tzva";
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break;
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case 6:
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if (Op1Val == 0 && Op2Val == 1)
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Asm = "dc\tivac";
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if (Op1Val == 0 && Op2Val == 2)
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Asm = "dc\tisw";
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break;
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case 10:
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if (Op1Val == 3 && Op2Val == 1)
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Asm = "dc\tcvac";
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else if (Op1Val == 0 && Op2Val == 2)
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Asm = "dc\tcsw";
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break;
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case 11:
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if (Op1Val == 3 && Op2Val == 1)
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Asm = "dc\tcvau";
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break;
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case 12:
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if (Op1Val == 3 && Op2Val == 1 &&
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(STI.getFeatureBits()[AArch64::HasV8_2aOps]))
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Asm = "dc\tcvap";
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break;
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case 14:
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if (Op1Val == 3 && Op2Val == 1)
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Asm = "dc\tcivac";
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else if (Op1Val == 0 && Op2Val == 2)
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Asm = "dc\tcisw";
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break;
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case 4: case 6: case 10: case 11: case 12: case 14:
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{
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const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
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if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
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return false;
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NeedsReg = true;
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Ins = "dc\t";
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Name = std::string(DC->Name);
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}
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break;
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// AT aliases
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case 8:
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switch (Op1Val) {
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default:
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break;
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case 0:
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switch (Op2Val) {
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default:
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break;
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case 0: Asm = "at\ts1e1r"; break;
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case 1: Asm = "at\ts1e1w"; break;
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case 2: Asm = "at\ts1e0r"; break;
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case 3: Asm = "at\ts1e0w"; break;
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}
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break;
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case 4:
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switch (Op2Val) {
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default:
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break;
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case 0: Asm = "at\ts1e2r"; break;
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case 1: Asm = "at\ts1e2w"; break;
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case 4: Asm = "at\ts12e1r"; break;
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case 5: Asm = "at\ts12e1w"; break;
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||||
case 6: Asm = "at\ts12e0r"; break;
|
||||
case 7: Asm = "at\ts12e0w"; break;
|
||||
}
|
||||
break;
|
||||
case 6:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "at\ts1e3r"; break;
|
||||
case 1: Asm = "at\ts1e3w"; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 9:
|
||||
switch (Op1Val) {
|
||||
default:
|
||||
break;
|
||||
case 0:
|
||||
if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "at\ts1e1rp"; break;
|
||||
case 1: Asm = "at\ts1e1wp"; break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 8: case 9: {
|
||||
const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
|
||||
if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
|
||||
return false;
|
||||
|
||||
NeedsReg = true;
|
||||
Ins = "at\t";
|
||||
Name = std::string(AT->Name);
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else if (CnVal == 8) {
|
||||
// TLBI aliases
|
||||
switch (CmVal) {
|
||||
default:
|
||||
break;
|
||||
case 3:
|
||||
switch (Op1Val) {
|
||||
default:
|
||||
break;
|
||||
case 0:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "tlbi\tvmalle1is"; break;
|
||||
case 1: Asm = "tlbi\tvae1is"; break;
|
||||
case 2: Asm = "tlbi\taside1is"; break;
|
||||
case 3: Asm = "tlbi\tvaae1is"; break;
|
||||
case 5: Asm = "tlbi\tvale1is"; break;
|
||||
case 7: Asm = "tlbi\tvaale1is"; break;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "tlbi\talle2is"; break;
|
||||
case 1: Asm = "tlbi\tvae2is"; break;
|
||||
case 4: Asm = "tlbi\talle1is"; break;
|
||||
case 5: Asm = "tlbi\tvale2is"; break;
|
||||
case 6: Asm = "tlbi\tvmalls12e1is"; break;
|
||||
}
|
||||
break;
|
||||
case 6:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "tlbi\talle3is"; break;
|
||||
case 1: Asm = "tlbi\tvae3is"; break;
|
||||
case 5: Asm = "tlbi\tvale3is"; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0:
|
||||
switch (Op1Val) {
|
||||
default:
|
||||
break;
|
||||
case 4:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 1: Asm = "tlbi\tipas2e1is"; break;
|
||||
case 5: Asm = "tlbi\tipas2le1is"; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
switch (Op1Val) {
|
||||
default:
|
||||
break;
|
||||
case 4:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 1: Asm = "tlbi\tipas2e1"; break;
|
||||
case 5: Asm = "tlbi\tipas2le1"; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 7:
|
||||
switch (Op1Val) {
|
||||
default:
|
||||
break;
|
||||
case 0:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "tlbi\tvmalle1"; break;
|
||||
case 1: Asm = "tlbi\tvae1"; break;
|
||||
case 2: Asm = "tlbi\taside1"; break;
|
||||
case 3: Asm = "tlbi\tvaae1"; break;
|
||||
case 5: Asm = "tlbi\tvale1"; break;
|
||||
case 7: Asm = "tlbi\tvaale1"; break;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "tlbi\talle2"; break;
|
||||
case 1: Asm = "tlbi\tvae2"; break;
|
||||
case 4: Asm = "tlbi\talle1"; break;
|
||||
case 5: Asm = "tlbi\tvale2"; break;
|
||||
case 6: Asm = "tlbi\tvmalls12e1"; break;
|
||||
}
|
||||
break;
|
||||
case 6:
|
||||
switch (Op2Val) {
|
||||
default:
|
||||
break;
|
||||
case 0: Asm = "tlbi\talle3"; break;
|
||||
case 1: Asm = "tlbi\tvae3"; break;
|
||||
case 5: Asm = "tlbi\tvale3"; break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
|
||||
if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
|
||||
return false;
|
||||
|
||||
NeedsReg = TLBI->NeedsReg;
|
||||
Ins = "tlbi\t";
|
||||
Name = std::string(TLBI->Name);
|
||||
}
|
||||
else
|
||||
return false;
|
||||
|
||||
if (Asm) {
|
||||
unsigned Reg = MI->getOperand(4).getReg();
|
||||
std::string Str = Ins + Name;
|
||||
std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
|
||||
|
||||
O << '\t' << Asm;
|
||||
if (StringRef(Asm).lower().find("all") == StringRef::npos)
|
||||
O << ", " << getRegisterName(Reg);
|
||||
}
|
||||
O << '\t' << Str;
|
||||
if (NeedsReg)
|
||||
O << ", " << getRegisterName(MI->getOperand(4).getReg());
|
||||
|
||||
return Asm != nullptr;
|
||||
return true;
|
||||
}
|
||||
|
||||
void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
||||
|
||||
@ -266,82 +266,84 @@ inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
|
||||
}
|
||||
} // end namespace AArch64CC
|
||||
|
||||
namespace AArch64AT{
|
||||
struct AT {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
};
|
||||
struct SysAlias {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
FeatureBitset FeaturesRequired;
|
||||
|
||||
SysAlias (const char *N, uint16_t E) : Name(N), Encoding(E) {};
|
||||
SysAlias (const char *N, uint16_t E, FeatureBitset F) :
|
||||
Name(N), Encoding(E), FeaturesRequired(F) {};
|
||||
|
||||
bool haveFeatures(FeatureBitset ActiveFeatures) const {
|
||||
return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
|
||||
}
|
||||
};
|
||||
|
||||
struct SysAliasReg : SysAlias {
|
||||
bool NeedsReg;
|
||||
SysAliasReg(const char *N, uint16_t E, bool R) : SysAlias(N, E), NeedsReg(R) {};
|
||||
};
|
||||
|
||||
namespace AArch64AT{
|
||||
struct AT : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_AT_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
|
||||
}
|
||||
namespace AArch64DB {
|
||||
struct DB {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
};
|
||||
|
||||
namespace AArch64DB {
|
||||
struct DB : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_DB_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64DC {
|
||||
struct DC {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
struct DC : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
|
||||
#define GET_DC_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64IC {
|
||||
struct IC {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
bool NeedsReg;
|
||||
struct IC : SysAliasReg {
|
||||
using SysAliasReg::SysAliasReg;
|
||||
};
|
||||
#define GET_IC_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64ISB {
|
||||
struct ISB {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
struct ISB : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_ISB_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64PRFM {
|
||||
struct PRFM {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
struct PRFM : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_PRFM_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64PState {
|
||||
struct PState {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
FeatureBitset FeaturesRequired;
|
||||
|
||||
bool haveFeatures(FeatureBitset ActiveFeatures) const {
|
||||
return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
|
||||
}
|
||||
struct PState : SysAlias{
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_PSTATE_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
}
|
||||
|
||||
namespace AArch64PSBHint {
|
||||
struct PSB {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
struct PSB : SysAlias {
|
||||
using SysAlias::SysAlias;
|
||||
};
|
||||
#define GET_PSB_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
@ -451,10 +453,8 @@ namespace AArch64SysReg {
|
||||
}
|
||||
|
||||
namespace AArch64TLBI {
|
||||
struct TLBI {
|
||||
const char *Name;
|
||||
uint16_t Encoding;
|
||||
bool NeedsReg;
|
||||
struct TLBI : SysAliasReg {
|
||||
using SysAliasReg::SysAliasReg;
|
||||
};
|
||||
#define GET_TLBI_DECL
|
||||
#include "AArch64GenSystemOperands.inc"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user