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RegisterCoalscer: Only coalesce complete reserved registers.
The coalescer eliminates copies from reserved registers of the form: %vregX = COPY %rY in the case where %rY is a reserved register. However this turns out to be invalid if only some of the subregisters are reserved (see also https://reviews.llvm.org/D26648). Differential Revision: https://reviews.llvm.org/D26687 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288428 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
parent
1750ec944f
commit
c139fdb8e4
@ -1571,11 +1571,17 @@ bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
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// Deny any overlapping intervals. This depends on all the reserved
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// register live ranges to look like dead defs.
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if (!MRI->isConstantPhysReg(DstReg)) {
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for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI)
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for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
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// Abort if not all the regunits are reserved.
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for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
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if (!MRI->isReserved(*RI))
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return false;
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}
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if (RHS.overlaps(LIS->getRegUnit(*UI))) {
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DEBUG(dbgs() << "\t\tInterference: " << PrintRegUnit(*UI, TRI) << '\n');
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return false;
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}
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}
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}
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// Skip any value computations, we are not adding new values to the
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@ -1,31 +0,0 @@
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# RUN: llc -mtriple=aarch64-- -run-pass=simple-register-coalescing %s -o - | FileCheck %s
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--- |
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define void @func() { ret void }
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...
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---
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# Check that we eliminate copies to/from constant physregs regardless of
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# "interfering" reads/writes.
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# CHECK: name: func
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# CHECK-NOT: COPY
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# CHECK: STRWui %wzr, %x1
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# CHECK-NOT: COPY
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# CHECK: STRXui %xzr, %x1
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# CHECK: %wzr = SUBSWri %w1, 0, 0
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name: func
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: gpr32 }
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body: |
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bb.0:
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%0 = COPY %wzr
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dead %wzr = SUBSWri %w1, 0, 0, implicit-def %nzcv
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STRWui %0, %x1, 0
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%1 = COPY %xzr
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dead %wzr = SUBSWri %w1, 0, 0, implicit-def %nzcv
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STRXui %1, %x1, 0
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%2 = SUBSWri %w1, 0, 0, implicit-def %nzcv
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%wzr = COPY %2
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...
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67
test/CodeGen/AArch64/regcoal-physreg.mir
Normal file
67
test/CodeGen/AArch64/regcoal-physreg.mir
Normal file
@ -0,0 +1,67 @@
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# RUN: llc -mtriple=aarch64-apple-ios -run-pass=simple-register-coalescing %s -o - | FileCheck %s
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--- |
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define void @func() { ret void }
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...
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---
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# Check coalescing of COPYs from reserved physregs.
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# CHECK-LABEL: name: func
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name: func
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr64 }
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- { id: 2, class: gpr64 }
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- { id: 3, class: gpr32 }
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- { id: 4, class: gpr64 }
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- { id: 5, class: gpr32 }
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- { id: 6, class: xseqpairsclass }
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body: |
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bb.0:
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; We usually should not coalesce copies from allocatable physregs.
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; CHECK: %0 = COPY %w7
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; CHECK: STRWui %0, %x1, 0
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%0 = COPY %w7
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STRWui %0, %x1, 0
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; It is fine to coalesce copies from reserved physregs
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; CHECK-NOT: COPY
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; CHECK: STRXui %fp, %x1, 0
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%1 = COPY %fp
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STRXui %1, %x1, 0
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; It is not fine to coalesce copies from reserved physregs when they are
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; clobbered.
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; CHECK: %2 = COPY %fp
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; CHECK: STRXui %2, %x1, 0
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%2 = COPY %fp
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%fp = SUBXri %fp, 4, 0
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STRXui %2, %x1, 0
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; Is is fine to coalesce copies from constant physregs even when they are
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; clobbered.
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; CHECK-NOT: COPY
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; CHECK: STRWui %wzr, %x1
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%3 = COPY %wzr
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dead %wzr = SUBSWri %w1, 0, 0, implicit-def %nzcv
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STRWui %3, %x1, 0
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; Is is fine to coalesce copies from constant physregs even when they are
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; clobbered.
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; CHECK-NOT: COPY
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; CHECK: STRXui %xzr, %x1
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%4 = COPY %xzr
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dead %wzr = SUBSWri %w1, 0, 0, implicit-def %nzcv
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STRXui %4, %x1, 0
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; Coalescing COPYs into constant physregs.
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; CHECK: %wzr = SUBSWri %w1, 0, 0
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%5 = SUBSWri %w1, 0, 0, implicit-def %nzcv
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%wzr = COPY %5
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; Only coalesce when the source register is reserved as a whole (this is
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; a limitation of the current code which cannot update liveness information
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; of the non-reserved part).
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; CHECK: %6 = COPY %xzr_x0
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; CHECK: HINT 0, implicit %6
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%6 = COPY %xzr_x0
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HINT 0, implicit %6
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...
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@ -78,40 +78,41 @@ define void @max_12_sgprs_14_input_sgprs(i32 addrspace(1)* %out1,
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ret void
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}
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; ALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}
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; The following test is commented out for now; http://llvm.org/PR31230
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; XALL-LABEL: max_12_sgprs_12_input_sgprs{{$}}
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; ; Make sure copies for input buffer are not clobbered. This requires
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; ; swapping the order the registers are copied from what normally
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; ; happens.
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; TOSMEM: s_mov_b32 s5, s11
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; TOSMEM: s_add_u32 m0, s5,
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; TOSMEM: s_buffer_store_dword vcc_lo, s[0:3], m0
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; XTOSMEM: s_mov_b32 s5, s11
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; XTOSMEM: s_add_u32 m0, s5,
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; XTOSMEM: s_buffer_store_dword vcc_lo, s[0:3], m0
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; ALL: SGPRBlocks: 2
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; ALL: NumSGPRsForWavesPerEU: 18
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define void @max_12_sgprs_12_input_sgprs(i32 addrspace(1)* %out1,
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i32 addrspace(1)* %out2,
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i32 addrspace(1)* %out3,
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i32 addrspace(1)* %out4,
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i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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store volatile i32 0, i32* undef
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%x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %x.0, i32 addrspace(1)* undef
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%x.3 = call i64 @llvm.amdgcn.dispatch.id()
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store volatile i64 %x.3, i64 addrspace(1)* undef
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%x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef
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store i32 %one, i32 addrspace(1)* %out1
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store i32 %two, i32 addrspace(1)* %out2
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store i32 %three, i32 addrspace(1)* %out3
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store i32 %four, i32 addrspace(1)* %out4
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ret void
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}
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; XALL: SGPRBlocks: 2
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; XALL: NumSGPRsForWavesPerEU: 18
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;define void @max_12_sgprs_12_input_sgprs(i32 addrspace(1)* %out1,
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; i32 addrspace(1)* %out2,
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; i32 addrspace(1)* %out3,
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; i32 addrspace(1)* %out4,
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; i32 %one, i32 %two, i32 %three, i32 %four) #2 {
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; store volatile i32 0, i32* undef
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; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.2 = call i32 @llvm.amdgcn.workgroup.id.z()
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; store volatile i32 %x.0, i32 addrspace(1)* undef
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; %x.3 = call i64 @llvm.amdgcn.dispatch.id()
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; store volatile i64 %x.3, i64 addrspace(1)* undef
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; %x.4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
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; store volatile i8 addrspace(2)* %x.4, i8 addrspace(2)* addrspace(1)* undef
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;
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; store i32 %one, i32 addrspace(1)* %out1
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; store i32 %two, i32 addrspace(1)* %out2
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; store i32 %three, i32 addrspace(1)* %out3
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; store i32 %four, i32 addrspace(1)* %out4
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; ret void
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;}
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declare i32 @llvm.amdgcn.workgroup.id.x() #1
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declare i32 @llvm.amdgcn.workgroup.id.y() #1
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